LTC4259ACGW-1#PBF Linear Technology, LTC4259ACGW-1#PBF Datasheet - Page 24

• Manufacturer Part Number: LTC4259ACGW-1#PBF
• Description: IC CTRLR POE QUAD AC DISC 36SSOP
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW-1#PBF

• Controller Type: Power over Ethernet Controller (POE)
• Interface: I²C
• Voltage - Supply: 3 V ~ 4 V
• Current - Supply: 2.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Package Type: SSOP
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LTC4259A-1
powered ports with AC disconnect enabled (and DC dis-
connect not enabled) will automatically disconnect. After
the LTC4259A-1 is reset (by power on, Reset All bit or the
RESET pin) the Osc Fail bit is set. Once the Osc Fail bit is
cleared, it will only be set by an invalid signal on the OSCIN
pin or another reset.
SERIAL DIGITAL INTERFACE
The LTC4259A-1 communicates with a host (master)
using the standard 2-wire interface as described in the
SMBus Specification Version 2.0 (available at http://
smbus.org). The SMBus is an extension of the I
and the LTC4259A-1 is also compatible with the I
standard. The Timing Diagrams (Figures 6 through 10)
show the timing relationship of the signals on the bus. The
two bus lines, SDA and SCL, must be high when the bus
is not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required on
these lines. If the SDA and SCL pull-ups are absent, not
connected to the same positive supply as the LTC4259A-
1’s V
to the LTC4259A-1, it is possible for the LTC4259A-1 to
see a START condition on the I
(INT) is only updated between I
if the LTC4259A-1 sees a START condition when it powers
up because the SCL and SDA lines were left floating, it will
not assert an interrupt (pull INT low) until it sees a STOP
condition on the bus. In a typical application the I
will immediately have traffic and the LTC4259A-1 will see
a STOP so soon after power up that this momentary
condition will go unnoticed.
Isolating the Serial Digital Interface
IEEE 802.3af requires that network segments be electri-
cally isolated from the chassis ground of each network
interface device. However, the network segments are not
required to be isolated from each other provided that the
segments are connected to devices residing within a
single building on a single power distribution system.
For simple devices such as small powered Ethernet
switches, the requirement can be met by using an iso-
lated power supply to power the entire device. This
implementation can only be used if the device has no
24
DD
pin, or are not activated when the power is applied
U
U
2
2
C transactions. Therefore
C bus. The interrupt pin
W
U
2
2
2
C bus,
C bus
C bus
electrically conducting ports other than twisted-pair Eth-
ernet. In this case, the SDAIN and SDAOUT pins of the
LTC4259A-1 can be connected together to act as a
standard I
If the device is part of a larger system, contains serial
ports, or must be referenced to protective ground for
some other reason, the Power over Ethernet subsystem
including the LTC4259A-1s must be electrically isolated
from the rest of the system. The LTC4259A-1 includes
separate pins (SDAIN and SDAOUT) for the input and
output functions of the bidirectional data line. This eases
the use of optocouplers to isolate the data path between
the LTC4259A-1s and the system controller. Figure 20
shows one possible implementation of an isolated inter-
face. The SDAOUT pin of the LTC4259A-1 is designed to
drive the inputs of an optocoupler directly, but a standard
I
signals into the optocouplers from the system controller
side. Schmitt triggers must be used to prevent extra
edges on transitions of SDA and SCL.
Bus Addresses and Protocols
The LTC4259A-1 is a read-write slave device. The master
can communicate with the LTC4259A-1 using the Write
Byte, Read Byte and Receive Byte protocols. The
LTC4259A-1’s primary serial bus address is
(010A
LTC4259A-1s also respond to the address (0110000)b,
allowing the host to write the same command into all of
the LTC4259A-1s on a bus in a single transaction. If the
LTC4259A-1 is asserting (pulling low) the INT pin, it will
also acknowledge the Alert Response Address (0001100)b
using the receive byte protocol.
The START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master (typically the host controller) signals the
beginning of communication with a slave device (like the
LTC4259A-1) by transmitting a START condition. A START
condition is generated by transitioning SDA from high to
low while SCL is high. A REPEATED START condition is
functionally the same as a START condition, but used to
extend the protocol for a change in data transmission
2
C device typically cannot. U1 is used to buffer I
3
A
2
A
2
1
C/SMBus SDA pin.
A
0
)b, as designated by pins AD3-AD0. All
4259a1fa
2
C