SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 114

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
10.1.2 Register Definitions
Receive FIFO (RFIFO)
Access: read
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) access
depending on the selected bus interface mode. The LSB is received first from the serial
interface.
In version 2 upwards, the size of the accessible part of RFIFO is determined by
programming the bits CCR4:RFT 1 … 0 (RFIFO threshold level). It can be reduced from
32 bytes (RESET value) down to 2 bytes (four values: 32, 16, 4, 2 bytes).
• Interrupt Controlled Data Transfer (Interrupt mode)
• DMA Controlled Data Transfer (DMA Mode)
Additionally, an RME interrupt is generated after the last byte has been transferred.
Further receiver DMA requests are blocked until an RMC command is issued in
response to RME.
The valid byte count of the whole frame can be determined by reading the RBCH, RBCL
registers following the RME interrupt.
Note: Addresses within the address space of the FIFO’s point all to the current data
Selected if DMA bit in XBCH is reset.
Up to 32 bytes/16 words of received data can be read from the RFIFO following an
RPF or an RME interrupt.
RPF Interrupt: A fixed number of bytes/words to be read (version 1: 32 bytes;
version 2 upward: 32, 16, 4, 2 bytes). The message is not yet complete.
RME Interrupt: The message is completely received. The Number of valid bytes is
determined by reading the RBCL, RBCH registers.
RFIFO is released by issuing the ‘Receive Message Complete’ command (RMC).
Selected if DMA bit in XBCH is set.
If the RFIFO is filled up to its threshold level, the ESCC2 autonomously requests a
block data transfer by DMA by activating the DRRn line until all read cycles are
performed (the DRRn line remains active up to the beginning of the last read cycle).
This forces the DMA controller to continuously perform bus cycles till all bytes/words
are transferred from the ESCC2 to the system memory (level triggered transfer mode
of DMA controller).
If the RFIFO contains less bytes/words than defined via threshold level (one short
frame or the last part of a long frame) the ESCC2 requests a block data transfer of
size equal to the amount of data to be transferred.
word/byte, i.e. the current data byte can be accessed with any address within the
32-byte range.
address: ch-A: 00 ... 1F
ch-B: 40 ... 5F
114
H
H
Detailed Register Description
SAB 82532/SAF 82532
HDLC Mode
07.96