SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 65

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

This feature can be profitably used e.g. for:
• user specific protocol variations
• line state monitoring, or
• test purposes, in particular for monitoring or intentionally generating HDLC protocol
Character or octet boundary synchronization can be achieved by using clock mode 1
with an external receive strobe input to pin CD.
5.4.5
If the extended transparent mode is selected, the ESCC2 supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to XFIFO, the command XREP.XTF.XME
via the CMDR register (bit 7 … 0 = ‘00101010’ = 2A
transmit the data stored in XFIFO via TxD pin.
The cyclic transmission continues until a reset command (CMDR: XRES) is issued, after
which continuous ‘1’s are transmitted.
Note: In DMA mode the command XREP and XTF has to be written to CMDR.
5.4.6
If data transfer from system memory to the ESCC2 is done by DMA (DMA bit in XBCH
set), the number of bytes to be transmitted is usually defined via the Transmit Byte Count
registers (XBCH, XBCL: bits XBC11 … XBC0).
Setting the ‘Transmit Continuously’ (XC) bit in XBCH, however, the byte count value is
ignored and the DMA interface of ESCC2 will continuously request for transmit data any
time 32 new bytes can be entered in XFIFO.
This feature can be used e.g. to transmit frames of length higher than the byte count
specified by XBCH, XBCL (frames with more than 4096 bytes).
Note: If the XC bit is reset during continuous transmission, the transmit byte count
Semiconductor Group
rule violations (e.g. wrong CRC)
becomes valid again, and the ESCC2 will request the amount of DMA transfers
programmed via XBC11 … XBC0. Otherwise, the continuous transmission and
the generation of DMA requests is stopped when a data underrun condition occurs
in XFIFO. Instead of CRC, continuous ‘1’s (IDLE) are transmitted thereafter.
Cyclic Transmission (fully transparent)
Continuous Transmission (DMA mode only)
65
H
) forces the ESCC2 to repeatedly
SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
07.96