SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 162

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
Interrupt Controlled Data Transfer (interrupt mode)
Selected if DMA bit in XBCH is reset.
Up to 32 bytes/16 words of received data can be read from the RFIFO following a RPF
or a TCD interrupt depending on the selected RFIFO mode (refer to RFC register):
RPF interrupt: A fixed number of bytes/words (programmed threshold level RFTH0, 1)
has to be read by the CPU.
TCD interrupt: Termination character detected. The received data stream is monitored
for ‘termination character’ (programmable via register TCR). The number of valid bytes
in RFIFO is determined by reading the RBCL register.
If necessary, the CPU can access the RFIFO by issuing RFIFO Read command
(CMDR.RFRD) before threshold level or the termination condition is reached. The
number of valid bytes is determined by reading the RBCL register. Additional
information: STAR:RFNE: RFIFO Not Empty.
DMA Controlled Data Transfer (DMA mode)
Selected if DMA bit in XBCH is set.
If the RFIFO contains the number of bytes/words defined via the threshold level, the
ESCC2 autonomously requests a DMA block data transfer by DMA by activating the
DRRn line until the last valid data is read (the DDRn line remains active up to the
beginning of the last read cycle).
This forces the DMA controller to continuously perform bus cycles till all data is
transferred from the ESCC2 to the system memory (level triggered transfer mode of
DMA controller). If the end condition (TCD) is reached, the same procedure as above is
performed. DRRn is activated until the termination character is transferred. A TCD
interrupt is issued after the last data has been transferred. Generation of further DMA
requests is blocked until TCD interrupt has been acknowledged by issuing an RMC
command. The valid byte count of the last block can be determined by reading the RBCL
register following the TCD interrupt.
Note: Addresses within the 32-byte address space of the FIFO’s point all to the same
byte/word, i.e. current data can be accessed with any address within the valid
scope.
162
Detailed Register Description
SAB 82532/SAF 82532
ASYNC Mode
07.96