ADM7001X-AC-T-1 Infineon Technologies, ADM7001X-AC-T-1 Datasheet
ADM7001X-AC-T-1
Specifications of ADM7001X-AC-T-1
ADM7001XACT1
ADM7001XACT1X
ADM7001XACT1X
ADM7001XACT1XP
SP000076255
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ADM7001X-AC-T-1 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... ISAC , ITAC ® ® ® QUAT , QuadFALC , SCOUT ® ® 10BaseV , 10BaseVX are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft ® Corporation, Linux of Linus Torvalds, Visio Incorporated. ® ® ® , ASP , DigiTape , DuSLIC ® ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Receive Path for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 ADM7001/X Block Diagram 10 Figure 2 Pin Diagram 11 Figure 3 100Base-X Block Diagram and Data Path 27 Figure 4 10Base-T Block Diagram and Data Path 32 Figure 5 RMII Signal Diagram 35 Figure 6 ...
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List of Tables Table 1 Abbreviations for Pin Type 12 Table 2 Abbreviations for Buffer Type 12 Table 3 Twisted Pair Interface, 5 Pins 13 Table 4 Digital Ground/Power, 7 Pins 14 Table 5 Ground and Power, 5 Pins 15 ...
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... The ADM7001 single chip one port 10/100M PHY, which is designed for today’s low cost and low power dual speed application. The ADM7001X is the environmentally friendly “green” package version. It supports auto sensing 10/100 Mbps ports with on-chip clock recovery and base line wander correction including integrated MLT-3 functionality for 100 Mbps operation, and also supports Manchester Code Converter with on chip clock recovery circuitry for 10 Mbps functionality ...
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Built-in Clock Generator and Power On Reset Signal to save system cost. • 48 LQFP without regulator. • Supports Power saving function. • Supports Parallel LED output. Data Sheet 9 ADM7001/X Data sheet Product Overview Rev. 1.07, 2005-11-25 ...
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Block Diagram Figure 1 ADM7001/X Block Diagram Data Sheet 10 ADM7001/X Data sheet Product Overview Rev. 1.07, 2005-11-25 ...
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Interface Description 2.1 Pin Diagram VCCO_25 GNDIK GNDO VCCIK_25 Figure 2 Pin Diagram 2.2 Pin Description Note: For those pins, which have multiple functions, pin name is separated by slash ("/"). If not specified, all signals are default to ...
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Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. AO Output. Analog levels. AI/O Input or Output. Analog levels. PWR ...
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Twisted Pair Interface, 5 Pins Table 3 Twisted Pair Interface, 5 Pins Pin or Ball Name No. 35 TXP 34 TXN 27 RXP 26 RXN 28 Power On Setting FXEN Fiber Mode SDP Data Sheet Pin Buffer Function Type ...
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Digital Ground/Power, 7 Pins Table 4 Digital Ground/Power, 7 Pins Pin or Ball Name No GNDO 2, 37 GNDIK 1, 18 VCCO_25 7 VCCIK_25 Data Sheet Pin Buffer Function Type Type D,GND Ground used by 3.3 V ...
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Ground and Power, 5 Pins Table 5 Ground and Power, 5 Pins Pin or Ball Name No. 41 VCC3IN 36 VCC25OUT 29 GNDTR 25 VCCA_25 32 VCCPLL_25 Data Sheet Pin Buffer Function Type Type A,PWR 3.3V Power input to ...
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Clock Input, 2 Pins Table 6 Clock Input, 2 Pins Pin or Ball Name No. 40 XI/OSCI 39 XO 2.2.5 MII/RMII/GPSI Interface, 16 pins Table 7 MII/RMII/GPSI Interface, 16 pins Pin or Ball Name No. 9 MII Mode TXCLK ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 14, 13, 12, MII Mode 11 TXD[3:0] RMII Mode TXD[3:0] GPSI Mode TXD[3:0] 10 MII Mode TXEN RMII Mode TXEN GPSI Mode TXEN 8 MII Mode TXER RMII ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 4 Power On Setting RMII_EN MII Mode RX_CLK RMII Mode CLKO50 GPSI Mode RX_CLK Data Sheet Pin Buffer Function Type Type I LVTTL RMII Enable. PD Used to ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 3 Power On Setting DIS_AMDIX_EN MII Mode RXDV RMII Mode CRSDV GPSI Mode LOW 45, 46, 47, Power On 48 Setting PHYAD[1:4] MII Mode RXD[3:0] RMII Mode RXD[1:0] ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 5 Power On Setting ISOLATE MII Mode RXER RMII Mode RXER GPSI Mode N/A 15 Power On Setting GPSI GPSI/MII Mode COL RMII Mode N/A Data Sheet Pin ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 16 Power On Setting REPEATER MII Mode CRS RMII Mode N/A GPSI Mode CRS Note: LVTTL: Low Voltage TTL Level Data Sheet Pin Buffer Function Type Type I ...
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Reset Pin Table 8 Reset Pin Pin or Ball Name No. 42 RESET# 2.2.7 Clock Signals, 6 Pins Table 9 Clock Signals, 6 pins Pin or Ball Name Pin No. Type 43 MDIO I/O 44 MDC I 19 Power ...
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Table 9 Clock Signals, 6 pins (cont’d) Pin or Ball Name Pin No. Type 24 PWRDOWN# I 38, 30 TEST[1:0] I Data Sheet Buffer Function Type LVTTL Low Power Operation. PU Note: When RESET# is reset to 0 and PWRDOWN# ...
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LED Interface, 4 Pins Table 10 LED Interface, 4 Pins Pin or Ball Name No. 20 Reserved LNKACT 21 Power On Setting SPD100 Normal Mode SPDLED Data Sheet Pin Buffer Function Type Type I TTL Reserved 8mA ...
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Table 10 LED Interface, 4 Pins (cont’d) Pin or Ball Name No. 22 Power On Setting DUPFUL Normal Mode DUPLED 23 Power On Setting ANEN Normal Mode COLLED 2.2.9 Regulator Control Table 11 Regulator Control Pin or Ball Name No. ...
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Function Description ADM7001/X integrates 100Base-X physical sub layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, and complete 10Base-T modules into a single chip for both 10 Mbps and 100 Mbps Ethernet operations. It also supports 100Base-FX operation through external ...
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The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The ADM7001/X implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data ...
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Decision Feedback techniques meets the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 140 meters. NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The ...
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Table 12 Look-up Table for Translating 5B Symbols into 4B Nibbles (cont’d) PCS Code-Group[4:0] Name 11010 C 11011 D 11100 E 11101 F 11111 I 11000 J 10001 K 01101 T 0111 R 00100 H 00000 V 00001 V 00010 ...
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Should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. Carrier Sense Carrier sense (CRS) for 100 Mbits/s operation ...
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Automatic “Signal_Detect“ Function Block When DIS_ANASDEN_N in register 18 is set to 0, ADM7001/X doesn't support SDP detection in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7001/X uses ...
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The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the ...
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Jabber Function The jabber function monitors the ADM7001/X output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once ...
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The basic mode control register at address 0 negotiation function. When auto negotiation is disabled, the speed selection bit (bit 13) controls switching between 10 Mbps or 100 Mbps operation, while the duplex mode ...
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Figure 5 RMII Signal Diagram 3.2.2 Receive Path for 100M Figure 6 shows the relationship among REFCLK, CRSDV, RXD and RXER while receiving a valid packet. Carrier sense is detected, which causes CRSDV to assert asynchronously to REFCLK. The received ...
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Figure 7 RMII Reception with False Carrier (100M Only) A receive symbol error event is shown in packet with the exception that all di-bits are substituted with the (01) pattern. Figure 8 RMII Reception with Symbol Error 3.2.3 Receive Path ...
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Figure 10 100M RMII Transmit Diagram Data Sheet 37 ADM7001/X Data sheet Function Description Rev. 1.07, 2005-11-25 ...
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Transmit Path for 10M In 10MBSE-T mode, each di-bit must be repeated 10 times by the MAC, TXEN and TXD[1:0] should be synchronous to REFCLK. When TXEN is asserted, it indicates that data on TXD[1:0] is valid for transmission. ...
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Figure 12 MII Signal Diagram 3.2.7 Receive Path for MII Figure 13 shows the relationship among RXCLK, RXDV, RXD and CRS during a reception of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001/X. When ADM7001/X ...
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Figure 14 MII Receive With False Carrier A receive symbol error event is shown in packet with the exception that all bits are substituted with the (0101) pattern. RXER will keep low in 10M Operation. Figure 15 MII Receive With ...
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Transmit Path for MII Figure 16 shows the relationship among TXCLK, TXEN and TXD[3:0] during a transmit event. TXEN and TXD[3:0] are synchronous to TXCLK, which is generated by MAC. TXCLK is running at 25M in 100M mode and ...
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Figure 18 GPSI Signal Diagram 3.2.10 Receive Path for GPSI Figure 19 shows the relationship among RXCLK, RXD and CRS during a receive of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001/X. When ADM7001/X detects ...
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Figure 20 GPSI Transmit Diagram 3.3 LED Display Register 19 is used for different mode led display. ADM7001/X provides power on LED self test to minimize and ease the system test cost. All LEDs will be Off during power on ...
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Table 17 Cable Distance LED Display LNKACT DUPCOL 3.4 Management Register Access The SMI consists of two pins, management data clock (MDC) and management data input/output (MDIO). The ADM7001/X is designed to ...
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Power On Reset Circuit is reset well. Setting the reset bit in the Basic Mode Control activates software reset Register (bit 15, register 0 ). This bit is self-clearing and, when set, will return a value of 1 ...
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Figure 23 Medium Detect Power Management Flow Chart Another way to reduce instant power is to separate the LED display period. All 4 LEDs will be divided into 4 time frame and each time frame occupies 1 us. One and ...
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Figure 24 Power and Ground Filtering Data Sheet VCCO_25 GNDIK ADM7001 GNDO VCCIK_25 QFP 48 47 ADM7001/X Data sheet Function Description VCC25OUT(CORE) GNDPLL VCCPLL_25 GNDTR VCCA_25 Rev. 1.07, 2005-11-25 ...
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Registers Description Table 18 Registers Address Space Module Base Address PHY 00 H Table 19 Registers Overview Register Short Name Register Long Name CR Control Register SR Status Register PHY_IR0 PHY Identifier Register 0 PHY_IR1 PHY Identifier Register 1 ...
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Table 20 Registers Access Types (cont’d) Mode Symbol Description Hardware (HW) Read only ro Register is set by HW (register between input and output -> one cycle delay) Read virtual rv Physically, there is no new register, the input of ...
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Control Register CR Control Register Field Bits Type RST 15 rwsc LPBK 14 rw SSL 13 rw ANEN 12 rw Data Sheet Offset 00 H Description RESET Setting this bit initiates the software reset function that resets the selected port, ...
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Field Bits Type PDN 11 rw ISO 10 rw RAN 9 rwsc DPLX SSM 6 ro Res 5:0 ro Data Sheet Description Power Down Enable Ored result with PI_PWRDN pin. Setting this bit high or ...
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Status Register SR Status Register Data Sheet Offset ADM7001/X Data sheet Registers Description Reset Value 7849 H Rev. 1.07, 2005-11-25 ...
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Field Bits Type TXF 14 TXH Res 9:7 SUPR 6 AN_C 5 Data Sheet Description 100Base-T4 Capable Set to 0 all the time to indicate that the PHY841F does not ...
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Field Bits Type RFD 4 ro ANEG 3 LINK 2 ro, llsc JAB 1 ro, lhsc XTND 0 ro Data Sheet Description Remote Fault Detect This bit is latched the RF bit in the auto negotiation link ...
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PHY Identifier PHY_IR0 PHY Identifier Register 0 Field Bits Type PHYID 15:0 ro PHY Identifier Register 1 PHY_IR1 PHY Identifier Register 1 Field Bits Type PHYID 15:10 ro MODEL 9:4 REVID 3:0 Data Sheet Offset 02 H Description PHY-ID IEEE ...
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Advertisement Advertisement Auto Negotiation Advertisement Register Field Bits Type Res Res 12 ro APD 11 rw PSE Data Sheet Offset 04 H Description Next Page This bit ...
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Field Bits Type TXF 8 rw TXD Sel 4:0 ro Auto Negotiation Link Partner Ability ANLPA Auto Negotiation Link Partner Ability Data Sheet Description 100Base-TX Full Duplex 0 NCFDO, Not capable of 100M Full duplex ...
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Field Bits Type NPG 15 ro ACK Res 12 LPAP 11 LPP 10 LPTA 9 TXF 8 TXD Sel 4:0 Auto Negotiation Expansion Register ANER Auto Negotiation Expansion Register Data Sheet Description ...
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Field Bits Type Res 15:5 ro PFLT 4 ro, lhsc LPNP 3 ro NXPG 2 PRCV 1 ro, lhsc LPAN 0 ro Reserved 0 Res0 Reserved 0 Field Bits Type Res 15:0 ro Table 22 Reserved Registers Register Short Name ...
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Table 22 Reserved Registers (cont’d) Register Short Name Register Long Name Res7 Reserved 7 Res8 Reserved 8 Res9 Reserved 9 Res10 Reserved 10 Res11 Reserved 11 Res12 Reserved 12 Res 13 Reserved 13 Generic PHY Control/Configuration Register Note: PHY Control/Configuration ...
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Field Bits Type Conv 8 rw Res 7:5 ro XOVEN 4 rw Res 3:2 rw En8 1 rw DPMG 0 rw Data Sheet Description Converter mode (only valid in rmii mode) 0 Conv_0, Normal Mode B 1 Conv_1, converter mode ...
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PHY 10M Module Configuration Register P10_MCR PHY 10M Module Configuration Register Field Bits Type Res 15 ro Data Sheet Offset 11 H Description Reserved Not Applicable 62 ADM7001/X Data sheet Registers Description Reset Value 0008 H Rev. 1.07, 2005-11-25 ...
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Field Bits Type SMS 14 rw Res 13 Res 12:11 ITCE 10 Res 9 Res 8:6 Res 5 APD 4 RJM 3 TJD 2 NTH 1 FRL 0 Data Sheet Description 10BASE-T Serial Mode Select. Only available when AD2106 works ...
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PHY 100M Module Control Register P100_MCR PHY 100M Module Control Register Field Bits Type Res 15:12 ro Res 11:10 rw Res 9:8 FxSel 7 Res 6:5 SCR 4 FEFI 3 CLE 2 ro IAC 1 rw Res 0 Data Sheet ...
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LED Configuration Register LCR LED Configuration Register Field Bits Type Res 15:12 ro LNKCTRL 11:8 ro COLCTRL 7:4 ro Data Sheet Offset 13 H Description Reserved Not Applicable Link/Act LED Control 0000 , Collision B 0001 , All Errors B ...
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Field Bits Type SPDCTRL 3:0 ro Data Sheet Description Speed LED Control 0000 , Collision B 0001 , All Errors B 0010 , Duplex B 0011 , Duplex/Collision B 0100 , Speed B 0101 , Link B 0110 , Transmit ...
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Interrupt Enable Register IER Interrupt Enable Register Field Bits Type Res 15:10 ro XCHG 9 rw SCIE 8 DCIE 7 PRIE 6 LSCE 5 SEIE 4 FCAR 3 TJIE 2 RJIE 1 EESE 0 Data Sheet Offset 14 H Description ...
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PHY Generic Status Register Note: PHY Status Registers start from ( reserves for further use) PGSR PHY Generic Status Register Field Bits Type Res 15:14 ro Res 13: FXEN 9 XOVER 8 CBLEN ...
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PHY Specific Status Register PSSR PHY Specific Status Register Field Bits Type Res 15:12 ro JRX 11 JTX 10 POL 9 POUT 8 PIN 7 DUP 6 SPD 5 LINK 4 RPAU 3 Data Sheet Offset 17 H Description Reserved ...
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Field Bits Type RDUP 2 ro RSPD 1 RANV 0 PHY Recommend Value Status Register PRVSR PHY Recommend Value Status Register Field Bits Type Res 15 ro RANV 14 FSEL 13 RSPD 12 RDUP 11 PREC 10 FEFD 9 XOVR ...
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Field Bits Type RSII PHYA 4:0 Interrupt Status Register ISR Interrupt Status Register Data Sheet Description RMII_SMII Interface 0 RSll_0, Non RMII_SMII Interface B 1 RSll_1, RMII or SMII Interface used B Repeater Mode Recommend Value ...
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Field Bits Type Res 15:10 cor XOVC 9 SPDC 8 DUPC 7 PREC 6 LNKC 5 SERR 4 FCAR 3 TJAB 2 RJAB 1 STRE 0 Receive Error Counter Register RECR Receive Error Counter Register Data Sheet Description Reserved Not ...
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Field Bits Type ERB 15:0 ro Chip ID Register CIR Chip ID Register Field Bits Type CHIPID 15:0 ro Data Sheet Description Error Counter Includes. 1 100MFC, 100M False Carrier H 2 100MSE, 100M Symbol Error H 3 10MTJ, 10M ...
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Electrical Characteristics 5.1 DC Characterization 5.1.1 Absolute Maximum Rating Table 23 Absolute Maximum Rating Parameter Symbol V 3.3 V Power Supply CC33 V 2.5 V Power Supply CC25 V Input Voltage IN V Output Voltage OUT T Storage Temperature ...
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AC Characteristics 5.2.1 XI/OSCI (Crystal/Oscillator) Timing (In MII Mode) WB;,B5,6( Figure 25 Crystal/Oscillator Timing Table 26 Crystal/Oscillator Timing Parameter 1) XI/OSCI Clock Period XI/OSCI Clock High XI/OSCI Clock Low XI/OSCI Clock Rise Time, V (max (min.) IL ...
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RMII Timing 5.3.1 REFCLK Input Timing (XI in RMII Mode) t_IN50_RISE Figure 26 REFCLK Input Timing Table 27 REFCLK Input Timing Parameter REFCLK Clock Period REFCLK Clock High REFCLK Clock Low REFCLK Clock Rise Time, V (max ...
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REFCLK Output Timing (CLKO50 in RMII Mode) t_OUT50_RISE Figure 27 REFCLK Output Timing Table 28 REFCLK Output Timing Parameter REFCLK Clock Period REFCLK Clock High REFCLK Clock Low REFCLK Clock Rise Time, V (max (min ...
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WB57B7;(0+ '$7$ 2Q 0HGLXP Figure 28 RMII Transmit Timing Table 29 RMII Transmit Timing Parameter TXD to REFCLK Rising Setup Time TXD to REFCLK Rising Hold Time TXEN asserts to data transmit to medium TXEN asserts to data transmit to ...
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Table 30 RMII Receive Timing Parameter Signal Detected on Medium to CRSDV High Signal Detected on Medium to CRSDV High IDLE Detected on Medium to CRSDV low IDLE Detected on Medium to CRSDV low CRSDV High to Receive Data on ...
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Table 31 REFCLK Input Timing Parameter RXCLK Clock Period(100M) 1) Note RXCLK Clock Period(10M) 2) Note RXCLK Clock High (100M) RXCLK Clock High (10M) RXCLK Clock Low (100M) RXCLK Clock Low (10M) RXCLK Clock Rise Time (max) to ...
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MII Receive Timing Figure 31 MII Receive Timing Table 32 MII Receive Timing Parameter Signal Detected on Medium to CRS High Signal Detected on Medium to CRS High Signal Detected on Medium to RXDV High Signal Detected on Medium ...
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TXCLK Output Timing Figure 32 TXCLK Output Timing Table 33 TXCLK Output Timing Parameter TXCLK Clock Period (100M) TXCLK Clock Period (10M) TXCLK Clock High (100M) TXCLK Clock High (10M) TXCLK Clock Low(100M) TXCLK Clock High (10M) TXCLK Clock ...
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Figure 33 MII Transmit Timing Table 34 MII Transmit Timing Parameter TXD to TXCLK Rising Setup Time TXD to TXCLK Rising Hold Time TXEN asserts to data transmit to medium (100M) TXEN asserts to data transmit to medium (10M) TXEN ...
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Figure 34 GPSI Receive Timing Table 35 GPSI Receive Timing Parameter 10M Receive Clock Period 10M Receive Clock High 10M Receive Clock Low Signal Detected on Medium to CRS High Signal Detected on Medium to Data Valid RXCLK rising to ...
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Table 36 GPSI Transmit Timing Parameter 10M Transmit Clock Period 10M Transmit Clock High 10M Transmit Clock Low TXD to TXCLK Rising Setup Time TXD to TXCLK Rising Hold Time TXEN asserts to data transmit to medium TXEN asserts to ...
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Table 37 Serial Management Interface (MDC/MDIO) Timing (cont’d) Parameter MDC Low MDC to MDIO Delay Time MDIO Input to MDC Setup Time MDIO Input to MDC Hold Time 5.7 Power On Configuration Timing Figure 37 Power On Configuration Timing Table ...
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Packaging ADM7001/X, Low Profile Quad Flat Package (LQFP) 48 Pin Figure 38 ADM7001/X,Low Profile Quad Flat Package (LQFP) Data Sheet 87 ADM7001/X Data sheet Packaging Rev. 1.07, 2005-11-25 ...
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Table 39 Dimensions for 100 Pin LQFP Package Symbol Millimeter (mm) Min. A – 0.08 1 Θ 0° Θ 0° 1 Θ 11° 2 ...
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Table 39 Dimensions for 100 Pin LQFP Package (cont’d) Symbol Millimeter (mm aaa bbb ccc ddd Data Sheet 0.50 BSC. 5.50 5.50 Tolerance of Form and Position 0.20 0.20 0.08 0.08 89 ADM7001/X Data sheet ...
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