PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 176

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
17.4.1.3
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 17-6. Once UOWN
is set, any data or control settings previously written
there by the user will be overwritten with data from the
SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
BDnSTAT<5:3>. The transfer count in the correspond-
ing BDnCNT register is updated. Values that overflow
the 8-bit register carry over to the two most significant
digits of the count, stored in BDnSTAT<1:0>.
17.4.2
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
REGISTER 17-6:
DS39632C-page 174
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-2
bit 1-0
UOWN
R/W-x
BD BYTE COUNT
BDnSTAT Register (SIE Mode)
UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer
Reserved: Not written by the SIE
PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
BC9:BC8: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
U-x
—
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)
W = Writable bit
‘1’ = Bit is set
R/W-x
PID3
R/W-x
PID2
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
17.4.3
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
For an endpoint starting location to be valid, it must fall
in the range of the USB RAM, 400h to 7FFh. No
mechanism is available in hardware to validate the BD
address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected
applications, the user may want to consider the
inclusion of software-based address validation in their
code.
PID1
BD ADDRESS VALIDATION
R/W-x
PID0
results.
© 2006 Microchip Technology Inc.
When
x = Bit is unknown
R/W-x
BC9
developing
R/W-x
BC8
bit 0
USB