PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 201

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.3.6
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device can be con-
figured to wake-up from Sleep.
19.3.7
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with the SS pin control
enabled (SSPCON1<3:0> = 04h). When the SS pin is
low, transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of a
FIGURE 19-4:
© 2006 Microchip Technology Inc.
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
SLAVE MODE
SLAVE SELECT
SYNCHRONIZATION
SLAVE SYNCHRONIZATION WAVEFORM
bit 7
bit 7
bit 6
PIC18F2455/2550/4455/4550
Preliminary
transmitted byte and becomes a floating output. Exter-
nal pull-up/pull-down resistors may be desirable
depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
Note 1: When the SPI module is in Slave mode
2: If the SPI is used in Slave mode with CKE
with
(SSPCON1<3:0> = 0100), the SPI module
will reset if the SS pin is set to V
set, then the SS pin control must be
enabled.
bit 7
bit 7
SS
pin
Next Q4 Cycle
after Q2
control
DS39632C-page 199
bit 0
bit 0
DD
enabled
.