PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 179

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.5
The USB module can generate multiple interrupt con-
ditions. To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<5>), in the microcontroller’s
interrupt logic.
FIGURE 17-8:
FIGURE 17-9:
© 2006 Microchip Technology Inc.
Note
Differential Data
USB Interrupts
1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
USB Reset
URSTIF
RESET
UEIR (Flag) and UEIE (Enable) Registers
CRC5EF
CRC5EE
BTOEF
BTOEE
BTSEF
BTSEE
START-OF-FRAME
Second Level USB Interrupts
PIDEE
PIDEF
CRC16EE
CRC16EF
USB INTERRUPT LOGIC FUNNEL
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
DFN8EF
DFN8EE
(USB Error Conditions)
SOFIF
SOF
SETUP
PIC18F2455/2550/4455/4550
DATA
Preliminary
STATUS
Figure 17-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 17-9 shows some common events
within a USB frame and their corresponding interrupts.
SETUPToken
STALLIE
STALLIF
UERRIE
UERRIF
ACTVIE
OUT Token
ACTVIF
URSTIF
URSTIE
Control Transfer
IDLEIE
From Host
IN Token
IDLEIF
From Host
SOFIE
TRNIE
From Host
SOFIF
TRNIF
UIR (Flag) and UIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
Empty Data
Transaction
From Host
From Host
To Host
(1)
Data
Data
From Host
To Host
To Host
ACK
ACK
ACK
SOF
1 ms Frame
USBIF
DS39632C-page 177
Transaction
Set TRNIF
Set TRNIF
Set TRNIF
Complete