PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 192

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
18.2
When the SPP is configured for USB operation, data
can be clocked directly to and from the USB peripheral
without intervention of the microcontroller; thus, no
process time is required. Data is clocked into or out
from the SPP with endpoint (address) information first,
followed by one or more bytes of data, as shown in
Figure 18-5. This is ideal for applications that require
isochronous, large volume data movement.
The following steps are required to set up the SPP for
USB control:
1.
2.
3.
4.
5.
6.
18.3
The SPP can also act as a parallel port for the
microcontroller. In this mode, the SPPEPS register
(Register 18-3) provides status and address write
control. Data is written to and read from the SPPDATA
register.
microcontroller, the SPP clock is driven by the
instruction clock (F
The following steps are required to set up the SPP for
microcontroller operation:
1.
2.
3.
FIGURE 18-5:
DS39632C-page 190
Note:
Configure the SPP as desired, including wait
states and clocks.
Set the SPPOWN bit for USB ownership.
Set the buffer descriptor starting address
(BDnADRL:BDnADRH) to FFFFh.
Set the KEN bit (BDnSTAT<5>) so the buffer
descriptor is kept indefinitely by the SIE.
Set the INCDIS bit (BDnSTAT<4>) to disable
automatic buffer address increment.
Set the SPPEN bit to enable the module.
Configure the SPP as desired, including wait
states and clocks.
Clear the SPPOWN bit.
Set SPPEN to enable the module.
Setup for USB Control
Setup for Microcontroller Control
When
If a USB endpoint is configured to use the
SPP, the data transfer type of that
endpoint must be isochronous only.
Endpoint
Address
OSC
the
/4).
TRANSFER OF DATA BETWEEN USB SIE AND SPP
SPP
Byte 0
is
owned
Byte 1
by
Byte 2
Preliminary
the
Byte 3
18.3.1
When owned by the microcontroller core, control can
generate an interrupt to notify the application when
each read and write operation is completed. The
interrupt flag bit is SPPIF (PIR1<7>) and is enabled by
the SPPIE bit (PIE1<7>). Like all other microcontroller
level interrupts, it can be set to a low or high priority.
This is done with the SPPIP bit (IPR1<7>).
18.3.2
Once configured, writing to the SPP is performed by
writing to the SPPEPS and SPPDATA registers. If the
SPP is configured to clock out endpoint address infor-
mation with the data, writing to the SPPEPS register
initiates the address write cycle. Otherwise, the write is
started by writing the data to the SPPDATA register.
The SPPBUSY bit indicates the status of the address
and the data write cycles.
The following is an example write sequence:
1.
2.
3.
4.
5.
Note:
Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing the
address. If address write is not used, then skip
to step 3.
Monitor the SPPBUSY bit to determine when the
address has been sent. The duration depends
on the wait states.
Write the data to the SPPDATA register. The
SPP automatically starts writing the data.
Monitor the SPPBUSY bit to determine when the
data has been sent. The duration depends on
the wait states.
Go back to steps 1 or 3 to write a new address
or data.
Write USB endpoint number to SPP
Write outbound USB data to SPP or
read inbound USB data from SPP
SPP INTERRUPTS
WRITING TO THE SPP
The SPPBUSY bit should be polled to
make certain that successive writes to the
SPPEPS or SPPDATA registers do not
overrun the wait time due to the wait state
setting.
Byte n
© 2006 Microchip Technology Inc.