PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 89

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 6-2:
© 2006 Microchip Technology Inc.
TBLPTRU
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIE
OSCFIF
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DECFSZ
BRA
BSF
BCF
CFGS
CMIP
CMIF
CMIE
Bit 6
—
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER1
WRITE_BUFFER_BACK
INTCON, GIE
EECON1, WREN
bit 21
USBIP
USBIF
USBIE
Bit 5
—
(1)
PIC18F2455/2550/4455/4550
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
EEIP
EEIE
Bit 4
EEIF
Preliminary
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
6.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 25.0 “Special Features of the
CPU” for more detail.
6.6
See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
Flash Program Operation During
Code Protection
TMR0IF
HLVDIP
HLVDIF
HLVDIE
WREN
Bit 2
PROTECTION AGAINST SPURIOUS
WRITES
TMR3IP
TMR3IF
TMR3IE
INT0IF
Bit 1
WR
CCP2IP
CCP2IE
CCP2IF
RBIF
Bit 0
RD
DS39632C-page 87
on page
Values
Reset
51
51
51
51
51
53
53
54
54
54