ICS1893Y-10 IDT, Integrated Device Technology Inc, ICS1893Y-10 Datasheet - Page 111

• Manufacturer Part Number: ICS1893Y-10
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893Y-10; 800-1934-5; ICS1893Y-10

8.3.4 MAC/Repeater Interface Pins
8.3.4.1 MAC/Repeater Interface Pins for Media Independent Interface
ICS1893Y-10 Rev F 1/20/04
This section lists pin descriptions for each of the following interfaces
•
•
•
Table 8-5
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII)
COL
CRS
MDC
Name
Section 8.3.4.1, “MAC/Repeater Interface Pins for Media Independent Interface”
Section 8.3.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface”
Section 8.3.4.3, “MAC/Repeater Interface Pins for 10M Serial Interface”
Pin
ICS1893Y-10 - Release
lists the MAC/Repeater Interface pin descriptions for the MII.
Number
Pin
49
50
31
Output
Output
Type
Input
Pin
Copyright © 2004, Integrated Circuit Systems, Inc.
Collision (Detect).
The ICS1893Y-10 asserts a signal on the COL pin when the ICS1893Y-10
detects receive activity while transmitting (that is, while the TXEN signal is
asserted by the MAC/repeater, that is, when transmitting). When the
mode is:
Carrier Sense.
When the ICS1893Y-10 mode is:
Management Data Clock.
The ICS1893Y-10 uses the signal on the MDC pin to synchronize the
transfer of management information between the ICS1893Y-10 and the
Station Management Entity (STA), using the serial MDIO data line. The
MDC signal is sourced by the STA.
Note:
1. The signal on the COL pin is not synchronous to either RXCLK or
2. In full-duplex mode, the COL signal is disabled and always remains
3. The COL signal is asserted as part of the signal quality error (SQE)
•
•
•
•
Note: The signal on the CRS pin is not synchronous to the signal on
10Base-T, the ICS1893Y-10 detects receive activity by monitoring the
un-squelched MDI receive signal.
100Base-TX, the ICS1893Y-10 detects receive activity when there are
two non-contiguous zeros in any 10-bit symbol derived from the MDI
receive data stream.
Half-duplex, the ICS1893Y-10 asserts a signal on its CRS pin when it
detects either receive or transmit activity.
Either full-duplex or Repeater mode, the ICS1893Y-10 asserts a signal
on its CRS pin only in response to receive activity.
TXCLK.
low.
test. This assertion can be suppressed with the SQE Test Inhibit bit (bit
18.2).
either the RXCLK or TXCLK pin.
All rights reserved.
111
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
January, 2004