ICS1893Y-10 IDT, Integrated Device Technology Inc, ICS1893Y-10 Datasheet - Page 67

• Manufacturer Part Number: ICS1893Y-10
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893Y-10; 800-1934-5; ICS1893Y-10

7.2.5 Low Power Mode (bit 0.11)
7.2.6 Isolate (bit 0.10)
7.2.7 Restart Auto-Negotiation (bit 0.9)
ICS1893Y-10 Rev F 1/20/04
This bit provides one way to control the ICS1893Y-10 low-power mode function. When bit 0.11 is logic:
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•
Note:
This bit controls the ICS1893Y-10 Isolate function. When bit 0.10 is logic:
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•
The default value for bit 0.10 depends upon the PHY address of
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•
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
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•
Zero, there is no impact to ICS1893Y-10 operations.
One, the ICS1893Y-10 enters the low-power mode. In this case, the ICS1893Y-10 disables all internal
functions and drives all MAC/repeater output pins low except for those that support the MII Serial
Management Port. In addition, the ICS1893Y-10 internally activates the TPTRI function to tri-state the
signals on the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Zero, there is no impact to ICS1893Y-10 operations.
One, the ICS1893Y-10 electrically isolates its data paths from the MAC/Repeater Interface. The
ICS1893Y-10 places all MAC/repeater output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL,
and CRS) in a high-impedance state and it isolates all MAC/repeater input signals (TXD[3:0], TXEN, and
TXER). In this mode, the Serial Management Interface continues to operate normally (that is, bit 0.10
does not affect the Management Interface).
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893Y-10 isolates itself
from the MAC/Repeater Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893Y-10 does not
isolate its MAC/Repeater Interface.
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893Y-10 isolates any attempt by the STA
to set bit 0.9 to logic one.
One (as set by an STA), the ICS1893Y-10 restarts the auto-negotiation process. Once the
auto-negotiation process begins, the ICS1893Y-10 automatically sets this bit to logic zero, thereby
providing the self-clearing feature.
ICS1893Y-10 - Release
There are two ways the ICS1893Y-10 can enter low-power mode. When entering low-power mode:
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•
By setting bit 0.11 to logic one, the ICS1893Y-10 maintains the value of all Management Register
bits except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their
default values instead. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
During a reset, the ICS1893Y-10 sets all management register bits to their default values.
Copyright © 2004, Integrated Circuit Systems, Inc.
and
Section 7.1.4.2, “Latching Low
All rights reserved.
67
Table
7-16. If the PHY address:
Chapter 7 Management Register Set
Bits”.)
January, 2004
Section