ICS1893Y-10 IDT, Integrated Device Technology Inc, ICS1893Y-10 Datasheet - Page 113

• Manufacturer Part Number: ICS1893Y-10
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893Y-10; 800-1934-5; ICS1893Y-10

ICS1893Y-10 Rev F 1/20/04
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
RXD0,
RXD1,
RXD2,
RXD3
RXDV
RXER
RXTRI
TXCLK
TXD0,
TXD1,
TXD2,
TXD3
Name
Pin
ICS1893Y-10 - Release
Number
Pin
35,
34,
33,
45,
46,
47,
32
36
39
41
43
48
Output
Output
Output
Output
Type
Input
Input
Pin
Copyright © 2004, Integrated Circuit Systems, Inc.
Receive Data 0–3.
Receive Data Valid.
The ICS1893Y-10 asserts RXDV to indicate to the MAC/repeater that data
is available on the MII Receive Bus (RXD[3:0]). The ICS1893Y-10:
Receive Error.
When the MAC/Repeater Interface is in:
Receive (Interface), Tri-State.
The input on this pin is from a MAC. When the signal on this pin is logic:
Transmit Clock.
The ICS1893Y-10 generates this clock signal to synchronize the transfer
of data from the MAC/Repeater Interface to the ICS1893Y-10. When the
mode is:
Transmit Data 0–3.
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
1. An ICS1893Y-10 asserts a signal on the RXER pin upon detection of a
2. The RXER signal always transitions synchronously with RXCLK.
3. The signal on RXER pin is conditioned by the RXTRI pin.
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Note:
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RXD0 is the least-significant bit and RXD3 is the most-significant bit of
the MII receive data nibble.
While the ICS1893Y-10 asserts RXDV, the ICS1893Y-10 transfers the
receive data signals on the RXD0–RXD3 pins to the MAC/Repeater
Interface synchronously on the rising edges of RXCLK.
Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see
100M Stream Interface: Synchronous Receive
De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
10M MII mode, RXER is not used.
100M MII mode, the ICS1893Y-10 asserts a signal on the RXER pin
when either of the following two conditions are true:
– Errors are detected during the reception of valid frames
– A False Carrier is detected
Low, the MAC indicates that it is not in a tri-state condition.
High, the MAC indicates that it is in a tri-state condition. In this case,
the ICS1893Y-10 acts to ensure that only one PHY is active at a time.
10Base-T, the TXCLK frequency is 2.5 MHz.
100Base-TX, the TXCLK frequency is 25 MHz.
TXD0 is the least-significant bit and TXD3 is the most-significant bit of
the MII transmit data nibble received from the MAC/repeater.
The ICS1893Y-10 samples its TXEN signal to determine when data is
available for transmission. When TXEN is asserted, the signals on a
the TXD[3:0] pins are sampled synchronously on the rising edges of
the TXCLK signal.
False Carrier so that repeater applications can prevent the
propagation of a False Carrier.
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113
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
Chapter 9.5.6, “MII /
Timing”.)
January, 2004