PIC16F716-I/SS Microchip Technology Inc., PIC16F716-I/SS Datasheet - Page 74

• Manufacturer Part Number: PIC16F716-I/SS
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 13 I/O, SSOP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/SS

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin SSOP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F716
9.10
The PIC16F716 devices have up to 7 sources of
interrupt. The Interrupt Control Register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE of the INTCON
register enables all un-masked interrupts when set, or
disables all interrupts when cleared. When bit GIE is
enabled, and an interrupt’s flag bit and mask bit are set,
the interrupt will vector immediately. Individual
interrupts can be disabled through their corresponding
enable bits in various registers. Individual interrupt bits
are set, regardless of the status of the GIE bit. The GIE
bit is cleared on Reset and when an interrupt vector
occurs.
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
FIGURE 9-13:
DS41206B-page 72
Note:
TMR1IF
TMR1IE
Interrupts
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
TMR2IF
TMR2IE
INTERRUPT LOGIC
ADIF
ADIE
CCP1IF
CCP1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
The peripheral interrupt flags are contained in the Spe-
cial Function Registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
Special Function Registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in Special
Function Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
© 2007 Microchip Technology Inc.
Wake-up (If in Sleep mode)
Interrupt to CPU