PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 11

PEF82912FV14XP

Manufacturer Part Number
PEF82912FV14XP
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF82912FV14XP

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
List of Figures
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Data Sheet
M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 78
M4, M5, M6 Bit Control in Transmit Direction . . . . . . . . . . . . . . . . . . . 78
CRC-Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Block Error Counter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Explanation of State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . 86
Standard NT State Machine (IEC-Q / NTC-Q Compatible)
(Footnotes: see
Simplified NT State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Pulse Streams Selecting Quiet Mode . . . . . . . . . . . . . . . . . . . . . . . . 100
Interrupt Structure U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . 104
S-Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . 120
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Complete Activation Initiated by Q-SMINT
Complete Deactivation Initiated by Exchange . . . . . . . . . . . . . . . . . . 123
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 127
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 129
Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
External Circuitry U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 133
External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 134
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Q-SMINT
Maximum Sinusoidal Ripple on Supply Voltage
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 199
IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . 200
IOM
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
®
-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . 200
®
I Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . 137
“Dependence of Outputs” on Page
®
I . . . . . . . . . . . . . . . . . . . 122
. . . . . . . . . . . . . . . 198
PEF 82912/82913
92) . . . . . . . . . 87
2001-03-30
Page

Related parts for PEF82912FV14XP