PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 195

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

M56
FILTER
M4
Filter
EOC
FILTER
4.11.3
The EOC Read register contains the last verified EOC message (M1-M3 bits) according
to the verification criterion selected in MFILT.EOC FILTER.
EOCR
Reset Value: 0FFF
Data Sheet
M56 FILTER
7
EOCR - EOC Read Register
controls the validation mode of the spare bits (M51, M52, M61) on a per bit
base (see
X0 =
X1 =
3-bit field which controls the validation mode of the M4 bits on a per bit
base (see
x00 =
x01 =
x10 =
x11 =
0xx =
1xx =
3-bit field which controls the processing of EOC messages and its
verification algorithm (see
100 =
001 =
010 =
011 =
6
Apply same filter to M5 and M6 bit data as programmed for M4 bit
data.
On Change
On Change
TLL coverage of M4 bit data
CRC coverage of M4 bit data
CRC and TLL coverage of M4 bit data
M4 bits towards state machine are covered by TLL.
M4 bits towards state machine are checked by the same
validation algorithm as programmed for the reporting to the system
interface (see
EOC automatic mode
EOC transparent mode without any filtering
EOC transparent mode with ‘on change’ filtering
EOC transparent mode with Triple-Last-Look (TLL) Filtering
H
Chapter
Chapter
5
2.4.4.3).
2.4.4.1).
Chapter
M4 FILTER
Chapter
4
read
181
2.4.4.2).
2.4.3.3).
3
2
Register Description
EOC FILTER
PEF 82912/82913
Address:
1
2001-03-30
0
63
H