PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 26

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 2
Data Sheet
Pin
48
60
59
64
61
3
4
49
16
55
41
17
42
Pin Definitions and Functions (cont’d)
Symbol
SR2
XIN
XOUT
AOUT
BOUT
AIN
BIN
VDDDET
MTI
PS1
PS2
ACT
TP1
Type
I
I
O
O
O
I
I
I
I
I
I
O
I
Function
S-Bus Receiver Input
Crystal 1:
Connected to a 15.36 MHz crystal
Crystal 2:
Connected to a 15.36 MHz crystal
Differential U-interface Output
Differential U-interface Output
Differential U-interface Input
Differential U-interface Input
VDD Detection:
This pin selects if the V
(’0’) and reset pulses are generated on pin
RSTO or whether it is deactivated (’1’) and an
external reset has to be applied on pin RST.
Metallic Termination Input.
Input to evaluate Metallic Termination pulses.
Tie to ’1’ if not used.
Power Status (primary).
The pin status is passed to the overhead bit
’PS1’ in the U frame to indicate the status of the
primary power supply (’1’ = ok).
Power Status (secondary).
The pin status is passed to the overhead bit
’PS2’ in the U frame to indicate the status of the
secondary power supply (’1’ = ok).
Activation LED.
Indicates the activation status of U- and S-
transceiver. Can directly drive a LED (4 mA).
Test Pin 1.
Used for factory device test.
Tie to V
12
SS
DD
detection is active
PEF 82912/82913
2001-03-30
Overview