PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 152

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEF 82912/82913
Register Description
After the Q-SMINT I has requested an interrupt by setting its INT pin to low, the host
must read first the Q-SMINT I interrupt status register (ISTA) in the associated interrupt
service routine. The INT pin of the Q-SMINT I remains active until all interrupt sources
are cleared. Therefore, it is possible that the INT pin is still active when the interrupt
service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
into the MASK register)
H
and writing back the old mask to the MASK register.
Data Sheet
138
2001-03-30