PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 191

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

26.0
PIC24F16KA102 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
REGISTER 26-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-1
bit 0
Note 1:
Note:
U-0
—
SPECIAL FEATURES
This selection should not be used in PIC24F08KA1XX devices.
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Watchdog
Integration and Programming Diagnostics,
refer to the individual sections of the
“PIC24F
provided below:
• Section 9. “Watchdog Timer (WDT)”
• Section 36. “High-Level Integration
• Section 33. “Programming and
(DS39697)
with Programmable High/Low-Voltage
Detect (HLVD)” (DS39725)
Diagnostics” (DS39716)
Unimplemented: Read as ‘0’
BSS<2:0>: Boot Segment Program Flash Code Protection bits
111 = No boot program Flash segment
011 = Reserved
110 = Standard security, boot program Flash segment starts at 200h, ends at 000AFEh
010 = High security boot program Flash segment starts at 200h, ends at 000AFEh
101 = Standard security, boot program Flash segment starts at 200h, ends at 0015FEh
001 = High security, boot program Flash segment starts at 200h, ends at 0015FEh
100 = Reserved
000 = Reserved
BWRP: Boot Segment Program Flash Write Protection bit
1 = Boot segment may be written
0 = Boot segment is write-protected
U-0
—
FBS: BOOT SEGMENT CONFIGURATION REGISTER
Family
Timer,
W = Writable bit
‘1’ = Bit is set
Reference
High-Level
U-0
—
Manual”
Device
U-0
—
Preliminary
PIC24F16KA102 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
26.1
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A complete list is
provided in Table 26-1. A detailed explanation of the
various bit functions is provided in Register 26-1 through
Register 26-8.
The address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
TABLE 26-1:
BSS2
FBS
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
Configuration
Register
Configuration Bits
R/W-1
BSS1
CONFIGURATION REGISTERS
LOCATIONS
x = Bit is unknown
R/W-1
BSS0
Address
F8000C
F8000A
F8000E
F80000
F80004
F80006
F80008
F80010
(1)
DS39927B-page 189
(1)
BWRP
R/W-1
bit 0