PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 93

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

9.0
The oscillator system for the PIC24F16KA102 family of
devices has the following features:
• A total of five external and internal oscillator options
• On-chip 4x Phase Locked Loop (PLL) to boost
FIGURE 9-1:
© 2009 Microchip Technology Inc.
Note:
as clock sources, providing 11 different clock
modes.
internal operating frequency on select internal and
external oscillator sources.
SOSCO
SOSCI
OSCO
OSCI
OSCILLATOR
CONFIGURATION
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended
reference source. For more information
on Oscillator Configuration, refer to the
“PIC24F Family Reference Manual”,
Section 38. “Oscillator with 500 kHz
Low-Power FRC” (DS39726).
Primary Oscillator
Secondary Oscillator
Oscillator
Oscillator
Oscillator
500 kHz
LPFRC
8 MHz
LPRC
FRC
PIC24F16KA102 FAMILY CLOCK DIAGRAM
to
SOSCEN
Enable
Oscillator
be
31 kHz (nominal)
a
comprehensive
CLKDIV<10:8>
Preliminary
PIC24F16KA102 FAMILY
4 x PLL
8 MHz
4 MHz
• Software-controllable switching between various
• Software-controllable postscaler for selective
• System frequency range declaration bits for EC
• A Fail-Safe Clock Monitor (FSCM) that detects clock
Figure 9-1 provides a simplified diagram of the oscillator
system.
clock sources.
clocking of CPU for system power savings.
mode. When using an external clock source, the
current consumption is reduced by setting the
declaration bits to the expected frequency range.
failure and permits safe application recovery or
shutdown.
ECPLL,FRCPLL
XTPLL, HSPLL
XT, HS, EC
FRCDIV
SOSC
LPRC
FRC
Clock Control Logic
Fail-Safe
Monitor
Clock
CLKDIV<14:12>
Reference Clock
WDT, PWRT, DSWDT
Clock Source Option
for Other Modules
Generator
REFOCON<15:8>
DS39927B-page 91
Peripherals
REFO
CLKO
CPU