STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 49

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
6.5
6.5.1
Power management
The STM32W108's power management system is designed to achieve the lowest deep
sleep current consumption possible while still providing flexible wakeup sources, timer
activity, and debugger operation. The STM32W108 has four main sleep modes:
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Wake sources
When in deep sleep the STM32W108 can be returned to the running state in a number of
ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2.
The following wake sources are available in both deep sleep 1 and 2.
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The following sources are only available in deep sleep 1 since the sleep timer is not active in
deep sleep 2.
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The following source is only available in deep sleep 0 since the SWJ is required to write
memory to set this wake source and the SWJ only has access to some registers in deep
sleep 0.
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The Wakeup Recording module monitors all possible wakeup sources. More than one
wakeup source may be recorded because events are continually being recorded (not just in
deep-sleep), since another event may happen between the first wake event and when the
STM32W108 wakes up.
Idle Sleep: Puts the CPU into an idle state where execution is suspended until any
interrupt occurs. All power domains remain fully powered and nothing is reset.
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is
fully powered down and the sleep timer is active
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to
save power. In this mode the sleep timer cannot wakeup the STM32W108.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep
sleep without powering down the core domain. Instead, the core domain remains
powered and all peripherals except the system debug components (ITM, DWT, FPB,
NVIC) are held in reset. The purpose of this sleep state is to allow STM32W108
software to perform a deep sleep cycle while maintaining debug configuration such as
breakpoints.
Wake on GPIO activity: Wake due to change of state on any GPIO.
Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.
Wake on serial controller 2: Wake due to a change of state on GPIO Pin PA2.
Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be
configured to point to any GPIO, this wake source is another means of waking on any
GPIO activity.
Wake on setting of CDBGPWRUPREQ: Wake due to setting the CDBGPWRUPREQ bit
in the debug port in the SWJ.
Wake on setting of CSYSPWRUPREQ: Wake due to setting the CSYSPWRUPREQ bit
in the debug port in the SWJ.
Wake on sleep timer compare A.
Wake on sleep timer compare B.
Wake on sleep timer wrap.
Wake on write to the WAKE_CORE register bit.
Doc ID 16252 Rev 8
System modules
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