STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 92

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial interfaces
9.9
9.9.1
9.9.2
92/209
31
15
31
15
30
14
30
14
Bits [7:0] SC_DATA: Transmit and receive data register. Writing to this register adds a byte to the transmit
SPI master mode registers
Serial data register (SCx_DATA)
Address offset: 0xC83C (SC1_DATA) and 0xC03C (SC2_DATA)
Reset value:
SPI configuration register (SCx_SPICFG)
Address offset: 0xC858 (SC1_SPICFG) and 0xC058 (SC2_SPICFG)
Reset value:
Bit 5 SC_SPIRXDRV: Receiver-driven mode selection bit (SPI master mode only). Clear this bit to
Bit 4 SC_SPIMST: Set this bit to put the SPI in master mode, clear this bit to put the SPI in slave
Bit 3 SC_SPIRPT: This bit controls behavior on a transmit buffer underrun condition in slave mode.
Bit 2 SC_SPIORD: This bit specifies the bit order in which SPI data is transmitted and received.
29
13
29
13
FIFO. Reading from this register takes the next byte from the receive FIFO and clears the
overrun error bit if it was set.
In UART mode (SC1 only), reading from this register loads the UART status register with the
parity and frame error status of the next byte in the FIFO, and clears these bits if the FIFO is
now empty.
initiate transactions when transmit data is available. Set this bit to initiate transactions when the
receive buffer (FIFO or DMA) has space.
mode.
Clear this bit to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to
this bit take effect when the transmit FIFO is empty and the transmit serializer is idle.
0: Most significant bit first.
28
12
28
12
Reserved
27
11
27
11
Reserved
0x0000 0000
0x0000 0000
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
Reserved
Reserved
23
23
7
7
22
22
6
6
1: Least significant bit first.
SC_SPI
RXDRV
21
21
rw
5
5
STM32W108CB, STM32W108HB
SC_S
PIMS
20
20
rw
T
4
4
SC_DATA
rw
SC_SP
IRPT
19
19
rw
3
3
SC_SP
IORD
18
18
rw
2
2
SC_SP
IPHA
17
17
rw
1
1
SC_SP
IPOL
16
16
rw
0
0