NAND01GR3B2CZA6E Micron Technology Inc, NAND01GR3B2CZA6E Datasheet
NAND01GR3B2CZA6E
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NAND01GR3B2CZA6E Summary of contents
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... NAND01G-B2C 1. x16 organization only available for MCP products. January 2010 NAND01GR3B2C NAND01GW3B2C NAND01GR4B2C NAND01GW4B2C 1-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, single level cell NAND flash memory – Hardware program/erase locked during ONFI 1.0 support – Cache read – Read signature – Read Data integrity – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.9 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.10 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6.1 8.6.2 9 Program and erase times and endurance cycles ...
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Contents 12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Electronic signature byte Table 14. Electronic signature byte/word Table 15. Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. Parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 17. NAND flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 18. Program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 45 Table 19. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 20. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 21. ...
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List of figures List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Each block can be programmed and erased up to 100,000 cycles (with ECC on). To extend the lifetime of NAND flash devices, the implementation of an error correction code (ECC) is mandatory. The devices feature a write protect pin that allows performing hardware protection against program and erase operations ...
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... NAND01G-B2C Timings Sequential Random Page Block access access Program erase time time time (typ) (max) (typ) (min) 25 µ µ 200 µ µ µ 1024-Mbit + 32Mbit NAND flash memory array Page buffer Y decoder Buffers I/O AI14291 Package VFBGA63 VFBGA153 TSOP48 (1) (1) ...
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NAND01G-B2C Figure 2. Logic diagram x16 organization only available for MCP. Table 3. Signal names Signal I/O8-15 Data input/outputs for x16 devices Data input/outputs, address inputs, or command inputs I/O0-7 for x8 and x16 devices AL ...
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Description Figure 3. TSOP48 connections 1. Only available for 3 V devices. 10/ NAND01G-B2C ...
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NAND01G-B2C Figure 4. VFBGA63 connections (top view through package Only available for 3 V devices ...
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Description Figure 5. VFBGA153 connections (top view through package ⎯ VSS C VSS A12 ...
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... Figure 6: Memory array 2.1 Bad blocks The NAND flash 2112-byte/1056-word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. The bad block Information is written prior to shipping (refer to management for more details) ...
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Memory array organization Figure 6. Memory array organization x8 DEVICES Block = 64 pages Page = 2112 bytes (2048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes 2,048 bytes 14/67 Block Page 8 bits 64 bytes ...
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NAND01G-B2C 3 Signal descriptions See Figure 2: Logic connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/outputs are used to input the selected address, output the data during a read operation or input a command or data during ...
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Signal descriptions 3.7 Write Enable (W) The Write Enable input, W, controls writing to the command interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a ...
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NAND01G-B2C 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see Typically, glitches of less than Chip Enable, Write Enable and Read Enable are ignored ...
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Bus operations Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 24 and 4.5 ...
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NAND01G-B2C Table 7. Address insertion, x16 devices I/O8- Bus (1) cycle I/O15 Any additional address input cycles will be ignored. Table 8. Address definitions, x8 devices Table ...
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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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NAND01G-B2C 6 Device operations The following section gives the details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode the Read command must be issued, see ...
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Device operations Figure 7. Read operations Add.N Add.N I/O 00h cycle 1 cycle 2 Command Address N input code 22/67 tBLBH1 Data Add.N Add.N 30h N cycle 3 cycle 4 Command Busy from address ...
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NAND01G-B2C Figure 8. Read operations (intercepted Col. I/O 00h Add 1 Column Address tWHBH tWHBL tBLBH1 Busy Col. Row Row 30h Add 2 Add 1 Add 2 Row Address Device operations tEHCLX ...
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Device operations Figure 9. Random data output during sequential data output Col Col Row I/O 00h Add 2 Add 1 Add 1 Command code 4 Add cycles Row Add 1,2 Col Add 1,2 24/67 ...
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NAND01G-B2C 6.2 Cache read The cache read operation is used to improve the read throughput by reading data using the cache register. Since the device has only one cache register, serial data output on one page may be executed while ...
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Device operations Figure 10. Cache read operation I/O 00h 30h tBLBH1 R/B 6.3 Page program The page program operation is the standard operation to program data to the memory array. Within a given block, the pages ...
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NAND01G-B2C 6.3.2 Random data input in a page During a sequential input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a Random Data Input command. The following two steps are required ...
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Device operations Figure 12. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 4 Add cycles Row Add 1,2 Col Add 1,2 Main area 28/67 tBLBH2 (Program Busy time) Address 85h Data Input ...
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NAND01G-B2C 6.4 Copy back program The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation ...
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Device operations Figure 14. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB 6.5 Block erase Erase operations are done one block at a time. An erase operation ...
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NAND01G-B2C 6.6 Reset The Reset command is used to reset the command interface and status register. If the Reset command is issued during any operation, the operation will be aborted was a program or erase operation that was ...
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Device operations 6.7.3 P/E/R controller bit (SR5) The program/erase/read controller bit indicates whether the P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is busy); when the bit ...
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NAND01G-B2C 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes three steps are required: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One bus write cycle ...
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... Read ONFI signature To recognize NAND flash devices that are compatible with ONFI 1.0 command set, the Read Electronic Signature command can be issued, followed by an address of 20h. The next four-byte output is the ONFI signature, which is the ASCII encoding of the ‘ONFI’ word. ...
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... The Read Parameter Page command retrieves the data structure that describes the NAND flash organization, features, timings and other behavioral parameters. This data structure enables the host processor to automatically recognize the NAND flash configuration of a device. The whole data structure is repeated at least five times. ...
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Device operations Figure 17. Read parameter page waveforms I/O0-7 ECh 00h R/B 36/ ... tBLBH1 NAND01G-B2C ... ai14409 ...
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NAND01G-B2C Table 16. Parameter page data structure Byte 0-3 4-5 6-7 8-9 10-31 32-43 44-63 64 65-66 67-79 (1) O/M Parameter page signature – Byte 0: 4Fh, ‘O’ M – Byte 1: 4Eh, ‘N’ – Byte 2: 46h, ‘F’ – ...
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Device operations Table 16. Parameter page data structure (continued) Byte 80-83 84-85 86-89 90-91 92-95 96-99 100 101 102 103-104 105-106 107 108-109 110 111 112 113 114 115-127 38/67 (1) O Number ...
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NAND01G-B2C Table 16. Parameter page data structure (continued) Byte 128 129-130 131-132 133-134 135-136 137-138 139-140 141-163 164-165 166-253 254-255 256-511 512-767 768 optional mandatory. (1) O/M M Timing mode support Bit 6 to bit ...
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Data protection 7 Data protection The device has hardware features to protect against program and erase operations. It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations recommended ...
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... This section gives information on the software algorithms that Numonyx recommends to implement to manage the bad blocks and extend the lifetime of the NAND device. NAND flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged ...
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... Software algorithms Table 17. NAND flash failure modes Operation Erase Program Read Figure 18. Bad block management flowchart Figure 19. Garbage collection Valid page Invalid page 42/67 Procedure Block replacement Block replacement or ECC START Block Address = Block 0 Increment Block Address Update Data NO Bad Block table ...
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... Error correction code Users must implement an error correction code (ECC) to identify and correct errors in data stored in NAND flash memories. The ECC implemented must be able to correct 1 bit every 512 bytes. Sensible data stored in spare area must be covered by ECC as well. 8.6 Hardware simulation models 8 ...
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Software algorithms These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to ...
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... Table 18. Table 18. Program, erase times and program erase endurance cycles Parameters Page program time Block erase time Program/erase cycles per block (with ECC) Data retention Program and erase times and endurance cycles NAND flash Min Typ 200 2 100,000 10 Unit Max 700 µ ...
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Maximum ratings 10 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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... Designers should check that the Parameter 1.8 V devices ) 3 V devices Grade Grade 6 1.8 V devices ) devices (2 1.8 V devices 3 V devices ref (1) Parameter Test condition (2) and C are not 100% tested. IN I/O DC and AC parameters NAND flash Min Max 1.7 1.95 2.7 3 – 8.35 5 Typ Max V ...
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... DC and AC parameters Figure 20. Equivalent testing circuit for AC characteristics measurement 48/67 NAND flash C L GND NAND01G-B2C ref 2R ref GND Ai11085 ...
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NAND01G-B2C Table 22. DC characteristics, 1.8 V devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high voltage IH V Input ...
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DC and AC parameters Table 24. AC characteristics for command, address, data input Alt. Symbol symbol t Address Latch Low to Write Enable High ALLWH t ALS t Address Latch High to Write Enable High ALHWH Command Latch High to ...
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NAND01G-B2C Table 25. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t Busy time during cache read BLBHx ...
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DC and AC parameters 1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 36 the time from W rising edge during the final address cycle to ...
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NAND01G-B2C Figure 22. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH W tALHWH (AL Setup time) AL tDVWH (Data Setup time) I/O Figure 23. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W ...
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DC and AC parameters Figure 24. Sequential data output after read AC waveforms E R tRLQV (R Accesstime) I/O tBHRL Low Low High. Figure 25. Serial access cycle after read, for frequency ...
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NAND01G-B2C Figure 26. Read status register AC waveforms CL tCLHWH E tELWH W R tDVWH (Data Setup time) I/O Figure 27. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to ...
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DC and AC parameters Figure 28. Page read operation AC waveforms CL E tWLWL Add.N Add.N I/O 00h cycle 1 cycle 2 Command Address N input code 56/67 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N ...
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NAND01G-B2C Figure 29. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program setup code tWLWL tWHWH Add.N Add.N Add.N N cycle 4 cycle 2 cycle 3 Address Input ...
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DC and AC parameters Figure 30. Block erase AC waveforms CL E tWLWL (Write Cycle time I/O 60h RB Block Erase Setup command Figure 31. Reset AC waveforms I/O FFh RB 58/67 tBLBH3 ...
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NAND01G-B2C Figure 32. Program/erase enable waveforms W tVHWH WP RB I/O Figure 33. Program/erase disable waveforms W tVLWH WP High RB I/O 11.1 Ready/Busy signal electrical characteristics Figure 35, Figure 34 signal. The value required for the resistor R So, ...
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DC and AC parameters Figure 34. Ready/Busy AC waveform Figure 35. Ready/Busy load circuit Figure 36. Resistor value versus waveform timings for Ready/Busy signal 25°C. 60/67 ready busy ...
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NAND01G-B2C 11.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD low ( guarantee ...
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Package mechanical 12 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in ...
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NAND01G-B2C Figure 39. VFBGA63 1. +15, 0.80 mm pitch, package outline FD1 BALL "A1" 1. Drawing is not to scale Table 27. VFBGA63 1.05 ...
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Package mechanical Figure 40. VFBGA153 0 132+21 3R14, 0.50 mm pitch, package outline and mechanical data 64/67 NAND01G-B2C MIN NOM MAX A 0.90 A1 0.15 0.58 A2 0.25 0.30 0.35 Øb D 7.90 8.00 ...
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... NAND01G-B2C 13 Ordering information Table 28. Ordering information scheme Example: Device type NAND flash memory Density 01G = 1 Gbit Operating voltage 1 2 Bus width ( x16 Family identifier B = 2112-byte/ 1056-word page Device options 2 = chip enable don't care enabled Product version B = second version ...
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Revision history 14 Revision history Table 29. Document revision history Date Version 24-Jun-2008 16-Jan-2009 23-Feb-2009 08-Jun-2009 29-Jan-2010 66/67 1 Initial release. Modified Section 8.5: Error correction 2 waveform, and Figure 36: Resistor value versus waveform timings for Ready/Busy signal. Removed ...
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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...