ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 105

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

EXTENDED FUNCTION TIMER (Cont’d)
7.3.3.7 Pulse Width Modulation Mode
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
Procedure
To use pulse width modulation mode select the fol-
lowing in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
And select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated
– Set the PWM bit.
– Select the timer clock CC[1:0] bits (see
Load the OC2R register with the value corre-
sponding to the period of the signal.
Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
The OC
ing application can be calculated using the follow-
ing formula:
Figure 62. Pulse Width Modulation Mode Timing
plied to the OCMP1 pin after a successful com-
parison with OC1R register.
plied to the OCMP1 pin after a successful com-
parison with OC2R register.
to the output compare 1 function.
Clock Control
i
R register value required for a specific tim-
OC i R Value =
COUNTER
OCMP1
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
Bits).
compare2
34E2
CC[1:0]
t
* INTCLK
FFFC FFFD FFFE
- 5
Table 22
OLVL2
ST92141 - EXTENDED FUNCTION TIMER (EFT)
Where:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See
Note: After a write instruction to the OC i HR regis-
ter, the output compare function is inhibited until
the OC i LR register is also written.
The OCF1 and OCF2 bits cannot be set by hard-
ware in PWM mode therefore the Output Compare
interrupt is inhibited. The Input Capture interrupts
are available.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
– t = Desired output compare period (seconds)
–
– CC1-CC0 = Timer clock prescaler
compare1
INTCLK
2ED0 2ED1 2ED2
Counter
= OC1R
Counter
= OC2R
When
When
= Internal clock frequency
OLVL1
Pulse Width Modulation cycle
compare2
OCMP1 = OLVL2
OCMP1 = OLVL1
34E2
Counter is reset
to FFFCh
Figure
OLVL2
FFFC
62).
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