ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 142

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.5.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPOE and MSTR
142/179
– The MODF bit is set and an SPI interrupt is
– The SPOE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the device
9
generated if the SPIE bit is set.
from the device and disables the SPI periph-
eral.
into slave mode.
the MODF bit is set.
bits may be restored to their original state during or
after this clearing sequence.
Hardware does not allow the user to set the SPOE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
7.5.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripher-
al.