LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 32

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
7.4.2 Interrupt sources
7.5 Event router
7.6 System Tick timer (SysTick)
7.7 On-chip static RAM
7.8 Boot ROM
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up
signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,
and Deep power-down modes. Individual events can be configured as edge or level
sensitive and can be enabled or disabled in the event router. The event router can be
battery powered.
The following events if enabled in the event router can create a wake-up signal and/or an
interrupt:
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
The LPC1850/30/20/10 support up to 200 kB SRAM with separate bus master access for
higher throughput and individual power control for low power operation.
The internal ROM memory is used to store the boot code of the LPC1850/30/20/10. After
a reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
AES capable parts also support:
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External pins WAKEUP0/1/2/3 and RESET
Alarm timer, RTC, WWDT, BOD interrupts
C_CAN and QEI interrupts
Ethernet, USB0, USB1 signals
Selected outputs of combined timers (SCT and timer0/1/3)
ROM memory size is 32 kB.
Supports booting from UART interfaces and external static memory such as NOR
flash, SPI flash, quad SPI flash.
Includes APIs for power control and OTP programming.
Includes SPIFI drivers.
Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
CMAC authentication on the boot image.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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