PCA9600D,112 NXP Semiconductors, PCA9600D,112 Datasheet - Page 4

• Manufacturer Part Number: PCA9600D,112
• Description: IC DUAL BI-DIR BUS BUFFER 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Bufferr

Specifications of PCA9600D,112

• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Current - Supply: 7.3mA
• Voltage - Supply: 2.5 V ~ 15 V
• Delay Time: 100ns
• Capacitance - Input: 10pF
• Tx/rx Type: I²C Logic
• Supply Voltage (max): 15 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285243112::PCA9600D::PCA9600D

NXP Semiconductors
PCA9600
Product data sheet
The logic threshold voltage levels at SX on this I
voltage V
When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal
3 mA with a V
I
SMBus or other systems that use TTL switching levels.
SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of
typically 300 μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX,
the sink capability of other connected drivers should be taken into account. Most TTL
devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the
requirement to ensure the 0.8 V TTL LOW.
For Fast-mode I
minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at −40 °C),
which forms part of the external driver loading. When selecting the pull-up it is necessary
to subtract the SX pin pull-up current, so, worst-case at −40 °C, the allowed pull-up can be
limited (by external drivers) to 2 mA.
When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher
specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA
at V
any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a
drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at
V
(5.5 V − 1 V) / 7 mA = 643 Ω. With 680 Ω pull-up, the Fm+ rise time of 120 ns maximum
can be met with total bus loading up to 200 pF.
The logic level on RX is determined from the power supply voltage V
LOW is below 40 % of V
threshold just slightly below half V
TX is an open-collector output without ESD protection diodes to V
via a pull-up resistor to a supply voltage in excess of V
exceeded. It has a larger current sinking capability than a normal I
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I
logic LOW at RX will cause I
with I
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I
when sinking 1 mA.
If the supply voltage V
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without V
presents no loading of external signals when V
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including V
2
OL
C-bus specification for all I
OL
= 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is
2
C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
= 1 V maximum. That 1 V complies with the bus LOW requirement (0.25V
CC
. The maximum I
OL
All information provided in this document is subject to legal disclaimers.
2
of 0.74 V maximum. That guarantees compliance with the Fast-mode
C-bus operation, the other connected I
CC
CC
Rev. 5 — 5 May 2011
fails, then neither the I
, and logic HIGH is above 55 % of V
2
2
2
C-bus pin SX to be pulled to a logic LOW level in accordance
C-bus voltages greater than 3 V, as well as compliance with
C-bus supply voltage is 15 V.
CC
CC
present. The input configuration on SX and RX also
).
2
C-bus by a LOW at RX is typically 0.64 V
CC
2
2
C-bus nor the TX output will be held
C-bus are independent of the IC supply
is not present.
CC
2
C-bus pin SX is below 0.425 V. A
2
, as long as the 15 V rating is not
C-bus parts may have the
Dual bidirectional bus buffer
CC
CC
(with a typical switching
2
C-bus device, being
. It may be connected
CC
CC
PCA9600
© NXP B.V. 2011. All rights reserved.
of the chip. Logic
= 0 V.
bus
) of
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