SLXT915QC.B3

Manufacturer Part NumberSLXT915QC.B3
DescriptionIC QUAD ETHERNET REPEATER 64-QFP
ManufacturerIntel
TypeRepeater
SLXT915QC.B3 datasheet
 


Specifications of SLXT915QC.B3

Rohs StatusRoHS non-compliantTx/rx TypeEthernet
Voltage - Supply4.75 V ~ 5.25 VCurrent - Supply240mA
Mounting TypeSurface MountPackage / Case64-QFP
Delay Time-Capacitance - Input-
Other names831529  
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Table 3.
Control, Status and Miscellaneous Signal Descriptions (Continued)
Pin
Symbol
I/O
18
LEDTP1
O
TP Port LED Drivers. These tri-state LED drivers use an alternating pulsed output to
19
LEDTP2
O
report TP port status. Each pin should be tied to a pair of LEDs (to the anode of one LED
and the cathode of a second LED). When connected this way, each pin reports five
20
LEDTP3
O
separate conditions (receive, transmit, link integrity, reverse polarity and auto partition).
21
LEDTP4
O
AUI Port LED Driver. This tri-state LED driver uses an alternating pulsed output to report
AUI port status. This pin should be tied to a pair of LEDs (to the anode of one LED and the
22
LEDAUI
O
cathode of a second LED). When connected this way, this pin reports five separate
conditions (receive, transmit, receive jabber, receive collision and auto partition).
4
5
8
NC
_
No Connects. Leave these pins unconnected (mandatory).
12
13
14
Table 4.
Inter-Repeater Backplane Signal Descriptions
Pin
Symbol
I/O
Backplane Clock. This 10 MHz clock synchronizes multiple repeaters on a common
backplane. In the synchronous mode, BCLKIO must be supplied to all repeaters from a
common external source. In the asynchronous mode, BCLKIO is supplied only when a
1
BCLKIO
I/O
repeater is outputting data to the bus. Each repeater outputs its internally recovered clock
when it takes control of the bus. Other repeaters on the backplane then sync to BCLKIO for
the duration of the transmission.
Backplane Synch Mode Select. This pin selects the backplane synch mode. When this
pin is left floating an internal pull-up defaults to the Asynchronous mode (A/SYNC High). In
the asynchronous mode 12 or more LXT915s can be connected on the backplane, and an
3
A/SYNC
I
external 10 MHz backplane clock source is not required. When the synchronous mode is
selected (A/SYNC tied Low), 32 or more LXT915s can be connected to the backplane and
an external 10 MHz backplane clock source is required.
Inter-Repeater Backplane Enable. This pin allows individual LXT915s to take control of
59
IRENA
I/O
the Inter-Repeater Backplane (IRB) data bus (IRDAT). The IRENA bus must be pulled up
locally by a 330 Ω resistor.
IRB Data. This pin is used to pass data between multiple repeaters on the IRB. The IRDAT
60
IRDAT
I/O
bus must be pulled up locally by a 330 Ω resistor.
IRB Driver Enable. The IRDEN pin is used to enable external bus drivers which may be
required in synchronous systems with large backplanes. This is an active low signal,
61
IRDEN
O
maintained for the duration of the data transmission. IRDEN must be pulled up locally by a
330 Ω resistor.
IRB Collision Flag Sense (IRCFS) and IRB Collision (IRCOL). These two pins are used
62
IRCFS
I/O
for collision signalling between multiple LXT915 devices on the IRB. Both the IRCFS bus
and the IRCOL bus must be pulled up globally with 330 Ω resistors.
63
IRCOL
I/O
precision resistor [±1%].)
1. IRENA and IRDAT can be buffered between boards in multi-board configurations. Where buffering is used, a 330 Ω pull-up
resistor can be used on each signal, on each board. Where no buffering is used, the total impedance should be no less than
330 Ω.
2. IRCFS and IRCOL cannot be buffered. In multi-board configurations, the total impedance on IRCOL should be no smaller
than 330 W. IRCFS should be pulled up only once, by a single 330 Ω, 1% resistor.
Datasheet
®
Intel
LXT915 Simple Quad Ethernet Repeater
Description
Description
1
1
2
1
(IRCFS requires a
9