QLX4300SIQSR Intersil, QLX4300SIQSR Datasheet - Page 4

• Manufacturer Part Number: QLX4300SIQSR
• Description: IC EQUALIZER REC 3.125GBPS 46QFN
• Manufacturer: Intersil
• Series: QLx™r

Specifications of QLX4300SIQSR

• Applications: Data Transport
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.1 V ~ 1.3 V
• Package / Case: 46-WQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descrptions
PIN NAME
CP2[C,B,A]
CP1[C,B,A]
OUT2[N,P]
OUT1[N,P]
EXPOSED
BGREF
ENB
CLK
PAD
PIN NUMBER
39, 40, 41
42, 43, 44
33, 34
36, 37
45
46
38
-
4
(Continued)
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and
CLK pins only when the ENB pin is ‘LOW’. Internally pulled down.
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI
is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and
20MHz. Internally pulled down.
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
QLx4300-S45
DESCRIPTION
November 19, 2009
FN6982.1