PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 42

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
5.2
5.2.1 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION
5.2.2 READ TRANSACTIONS
When the bridge detects an address parity error on the secondary interface, the following events occur:
DATA PARITY ERRORS
When forwarding transactions, the bridge attempts to pass the data parity condition from one interface
to the other unchanged, whenever possible, to allow the master and target devices to handle the error
condition.
The following sections describe, for each type of transaction, the sequence of events that occurs when a
parity error is detected and the way in which the parity condition is forwarded across the bridge.
SPACE
When the bridge detects a data parity error during a Type 0 configuration write transaction to the bridge
configuration space, the following events occur:
If the parity error response bit is set in the command register, the bridge asserts P_TRDY# and writes
the data to the configuration register. The bridge also asserts P_PERR#. If the parity error response bit
is not set, the bridge does not assert P_PERR#.
The bridge sets the detected parity error bit in the status register, regardless of the state of the parity
error response bit.
When the bridge detects a parity error during a read transaction, the target drives data and data parity,
and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when the
bridge detects a read data parity error on the secondary bus, the following events occur:
If the parity error response bit is set in the bridge control register, the bridge does not claim the
transaction with S_DEVSEL#; this may allow the transaction to terminate in a master abort. If
parity error response bit is not set, the bridge proceeds normally and accepts transaction if it is
directed to or across the bridge.
The bridge sets the detected parity error bit in the secondary status register.
The bridge asserts P_SERR# and sets signaled system error bit in status register, if both of the
following conditions are met:
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
Bridge asserts S_PERR# two cycles following the data transfer, if the secondary interface parity
error response bit is set in the bridge control register.
Bridge sets the detected parity error bit in the secondary status register.
Bridge sets the data parity detected bit in the secondary status register, if the secondary interface
parity error response bit is set in the bridge control register.
Bridge forwards the bad parity with the data back to the initiator on the primary bus. If the data
with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
Page 42 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A