PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 71

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.34 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER –
13.2.35 P_SERR# EVENT DISABLE REGISTER – OFFSET 64h
OFFSET 4Ch
Bit
4
15:5
Bit
31:28
Bit
0
1
2
Function
Memory Read
Data Buffer
Control
Reserved
Function
Secondary bus
arbiter
preemption
control
Function
Reserved
Posted Write
Parity Error
Posted Write
Non-Delivery
Type
RW
RO
Type
RW
Type
RO
RW
RW
Reserved. Returns 0 when read. Reset to 0
Description
Ability to control bridge’s behavior when the data buffer is empty
0: start returning memory read data right away and inserts wait states if the data
buffer is empty
1: start returning memory read data after 1 cache line of data and disconnects the
master if the data buffer is empty
Reset to 0
Description
Controls the number of clock cycles after frame is asserted before preemption is
enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles after FRAME asserted
0001: Preemption enabled after 1 clock cycle after FRAME asserted
0010: Preemption enabled after 2 clock cycles after FRAME asserted
0011: Preemption enabled after 4 clock cycles after FRAME asserted
0100: Preemption enabled after 8 clock cycles after FRAME asserted
0101: Preemption enabled after 16 clock cycles after FRAME asserted
0110: Preemption enabled after 32 clock cycles after FRAME asserted
0111: Preemption enabled after 64 clock cycles after FRAME asserted
Description
Reserved. Returns 0 when read. Reset to 0
Controls bridge’s ability to assert P_SERR# when it is unable to transfer any read
data from the target after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted if this event occurs.
Reset to 0
Controls bridge’s ability to assert P_SERR# when it is unable to transfer delayed
write data after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the
command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Page 71 of 82
24
attempts.
24
attempts.
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A