PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 5

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
TABLE OF CONTENTS
1
2
3
1.1
1.2
1.3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.1
3.2
3.3
SIGNAL DEFINITIONS.............................................................................................................................11
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
PCI BUS OPERATION...............................................................................................................................16
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.7.1
2.7.2
2.7.3
2.7.4
2.8.1
2.8.2
2.8.3
2.8.4
ADDRESS DECODING..............................................................................................................................33
3.2.1
3.2.2
3.3.1
3.3.2
SIGNAL TYPES....................................................................................................................................11
SIGNALS ..............................................................................................................................................11
PIN LIST – 128-PIN QFP......................................................................................................................15
TYPES OF TRANSACTIONS..............................................................................................................16
SINGLE ADDRESS PHASE ................................................................................................................17
DEVICE SELECT (DEVSEL#) GENERATION..................................................................................17
DATA PHASE.......................................................................................................................................17
WRITE TRANSACTIONS ...................................................................................................................17
READ TRANSACTIONS .....................................................................................................................20
CONFIGURATION TRANSACTIONS ...............................................................................................24
TRANSACTION TERMINATION.......................................................................................................27
ADDRESS RANGES ............................................................................................................................33
I/O ADDRESS DECODING .................................................................................................................33
MEMORY ADDRESS DECODING.....................................................................................................35
PRIMARY BUS INTERFACE SIGNALS ...................................................................................11
SECONDARY BUS INTERFACE SIGNALS .............................................................................12
CLOCK SIGNALS ........................................................................................................................14
MISCELLANEOUS SIGNALS ....................................................................................................14
POWER AND GROUND..............................................................................................................14
MEMORY WRITE TRANSACTIONS.........................................................................................18
MEMORY WRITE AND INVALIDATE .....................................................................................18
DELAYED WRITE TRANSACTIONS ........................................................................................19
WRITE TRANSACTION BOUNDARIES...................................................................................20
BUFFERING MULTIPLE WRITE TRANSACTIONS..............................................................20
FAST BACK-TO-BACK TRANSACTIONS ................................................................................20
PREFETCHABLE READ TRANSACTIONS .............................................................................21
DYNAMIC PREFETCHING CONTROL....................................................................................21
NON-PREFETCHABLE READ TRANSACTIONS ...................................................................21
READ PREFETCH ADDRESS BOUNDARIES ........................................................................22
DELAYED READ REQUESTS ...................................................................................................22
DELAYED READ COMPLETION WITH TARGET .................................................................23
DELAYED READ COMPLETION ON INITIATOR BUS.........................................................23
FAST BACK-TO-BACK READ TRANSACTIONS ....................................................................24
TYPE 0 ACCESS TO PI7C8140A................................................................................................25
TYPE 1 TO TYPE 0 CONVERSION ...........................................................................................25
TYPE 1 TO TYPE 1 FORWARDING ..........................................................................................26
SPECIAL CYCLES.......................................................................................................................27
MASTER TERMINATION INITIATED BY PI7C8140A ..........................................................28
MASTER ABORT RECEIVED BY PI7C8140A .........................................................................29
TARGET TERMINATION RECEIVED BY PI7C8140A ...........................................................29
TARGET TERMINATION INITIATED BY PI7C8140A...........................................................31
I/O BASE AND LIMIT ADDRESS REGISTER .........................................................................34
ISA MODE ....................................................................................................................................34
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ..................................35
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ..........................36
Page 5 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A