PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 50

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
6
6.1
6.2
The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of
these events have additional device-specific disable bits in the P_SERR# event disable register that
make it possible to mask out P_SERR# assertion for specific events. The master timeout condition has a
SERR# enable bit for that event in the bridge control register and therefore does not have a device-
specific disable bit.
PCI BUS ARBITRATION
The bridge must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it
must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for
the primary bus resides external to the bridge, typically on the motherboard. For the secondary PCI bus,
the bridge implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be
used instead. This chapter describes primary and secondary bus arbitration.
PRIMARY PCI BUS ARBITRATION
The bridge implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI
bus arbitration. The bridge asserts P_REQ# when forwarding transactions upstream; that is, it acts as
initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the
upstream direction, either posted write data or delayed transaction requests, the bridge keeps P_REQ#
asserted. However, if a target retry, target disconnect, or a target abort is received in response to a
transaction initiated by the bridge on the primary PCI bus, the bridge de-asserts P_REQ# for two PCI
clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been
completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after the bridge has
asserted P_REQ#, the bridge initiates a transaction on the primary bus during the next PCI clock cycle.
When P_GNT# is asserted to the bridge when P_REQ# is not asserted, the bridge parks P_AD, P_CBE,
and P_PAR by driving them to valid logic levels. When the primary bus is parked at the bridge and the
bridge has a transaction to initiate on the primary bus, the bridge starts the transaction if P_GNT# was
asserted during the previous cycle.
SECONDARY PCI BUS ARBITRATION
The bridge implements an internal secondary PCI bus arbiter. This arbiter supports four external
masters on the secondary bus in addition to the PI7C8140A. The secondary arbiter supports a
programmable 2-level rotating algorithm. If the bridge detects that an initiator has failed to assert
S_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-
asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in
the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no
earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, S_FRAME# or
Delayed read data cannot be transferred from target after 2
received)
Master timeout on delayed transaction
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(default) attempts (2
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
24
target retries
PI7C8140A