DS64EV400SQX/NOPB National Semiconductor, DS64EV400SQX/NOPB Datasheet - Page 2

• Manufacturer Part Number: DS64EV400SQX/NOPB
• Description: IC EQUALIZER QUAD PROGR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS64EV400SQX/NOPB

• Applications: Displays
• Package / Case: 48-LLP
• Mounting Type: Surface Mount
• For Use With: DS64EV400-EVK - BOARD EVAL 6.4GBPS QUAD EQUALIZR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Interface: -
• Other names: DS64EV400SQX

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HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
IN_1+
IN_1–
IN_2+
IN_2–
IN_3+
IN_3–
OUT_0+
OUT_0–
OUT_1+
OUT_1–
OUT_2+
OUT_2–
OUT_3+
OUT_3–
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
DEVICE CONTROL
EN0
EN1
EN2
EN3
FEB
SD0
SD1
SD2
SD3
POWER
V
GND
DAP
Pin Name
DD
Pin Descriptions
3, 6, 7,
10, 13,
22, 24,
27, 30,
15, 46
31, 34
Pin #
PAD
11
12
36
35
33
32
29
28
26
25
37
14
23
44
42
40
38
21
45
43
41
39
1
2
4
5
8
9
O, LVCMOS
O, LVCMOS
O, LVCMOS
O, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I/O, Type
O, CML
O, CML
O, CML
O, CML
I, CML
I, CML
I, CML
I, CML
Power
Power
Power
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to V
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to V
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to V
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to V
BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
internally pulled high. BST_1 and BST_0 are internally pulled low.
Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register
bits. FEB is internally pulled High.
Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
V
path. A 0.01μF bypass capacitor should be connected between each V
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
DD
= 2.5V ± 5% or 3.3V ± 10%. V
2
DD
pins should be tied to V
Description
DD
DD
DD
DD
and OUT_0- to V
and OUT_1- to V
and OUT_2- to V
and OUT_3- to V
DD
plane through low inductance
DD
DD
DD
DD
.
.
.
.
DD
pin to GND planes.