DS64EV400SQX/NOPB National Semiconductor, DS64EV400SQX/NOPB Datasheet - Page 6

IC EQUALIZER QUAD PROGR 48-LLP

DS64EV400SQX/NOPB

Manufacturer Part Number
DS64EV400SQX/NOPB
Description
IC EQUALIZER QUAD PROGR 48-LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of DS64EV400SQX/NOPB

Applications
Displays
Package / Case
48-LLP
Mounting Type
Surface Mount
For Use With
DS64EV400-EVK - BOARD EVAL 6.4GBPS QUAD EQUALIZR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Interface
-
Other names
DS64EV400SQX
www.national.com
SIGNAL DETECT and ENABLE TIMING
t
t
t
t
ZISD
IZSD
OZOED
ZOED
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at V
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mV
Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock-like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (J
1; J
Note 9: The V
Symbol
IN
is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
DD2.5
Input OFF to ON detect — SD
Output High Response Time
Input ON to OFF detect — SD
Output Low Response Time
EN High to Output ON Response
Time
EN Low to Output OFF Response
Time
is V
DD
= 2.5V ± 5% and V
Parameter
P-P
sine wave) under typical conditions.
DD3.3
is V
DD
= 3.3V ± 10%.
Response time measurement at
V
100 Mbps, 40” of 6 mil microstrip
FR4
(Figure 1, 4), (Note 7)
Response time measurement at
EN input to V
100 Mbps, 40” of 6 mil microstrip
FR4
(Figure 1, 5), (Note 7)
IN
to SD output, V
DD
= 3.3V or 2.5V, T
OUT
2
Conditions
– J
O
IN
, V
6
2
). J
IN
IN
OUT
= 800 mV
= 800 mV
A
is the random jitter at equalizer outputs in ps-rms, see point C of Figure
= 25°C., and at the Recommended Operation Conditions at the time of
P-P
P-P
,
,
Min
(note 2)
Typ
400
150
35
5
Max
Units
ns
ns
ns
ns

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