MT47H128M16RT-3:C Micron Technology Inc, MT47H128M16RT-3:C Datasheet - Page 32

• Manufacturer Part Number: MT47H128M16RT-3:C
• Description: IC DDR2 SDRAM 2GB 667HZ 84FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H128M16RT-3:C

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (128M x 16)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 11: DDR2 I
Notes 1–7 apply to the entire table
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. F 12/10 EN
Parameter/Condition
Burst refresh current:
command at every
HIGH, CS# is HIGH between valid commands; Oth-
er control and address bus inputs are switching;
Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read current: All
bank interleaving reads, I
CL (I
(I
t
id commands; Address bus inputs are stable dur-
ing deselects; Data bus inputs are switching (see
Table 9 (page 28) for details)
RCD (I
DD
),
DD
t
RC =
), AL =
DD
); CKE is HIGH, CS# is HIGH between val-
t
RC (I
t
RCD (I
DD
),
t
DD
RFC (I
DD
t
RRD =
Notes:
) - 1 x
Specifications and Conditions (Die Revision C) (Continued)
t
CK =
DD
OUT
) interval; CKE is
t
RRD (I
t
= 0mA; BL = 4, CL =
CK (I
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
CK (I
UDQS#. I
operated outside of the range 0°C ≤ T
DD
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
When
T
DD
DD
DD1
DD
DD
C
C
DD
);
),
≤ 0°C
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
≥ 85°C
); refresh
= +1.8V ±0.1V, V
t
CK =
t
RCD =
DD4R
DD
, and I
t
CK
values must be met with all combinations of EMR bits 10 and 11.
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
IN
IN
DD
DD
DD7
≤ V
≥ V
Symbol
values must be derated (I
conditions:
I
IL(AC)max
IH(AC)min
require A12 in EMR1 to be enabled during testing.
I
I
I
DD6L
DD5
DD6
DD7
DDQ
REF
= +1.8V ±0.1V, V
I
must be derated by 2%; and I
7%.
I
must be derated by 2%; I
slow must be derated by 30%; and I
80% (I
refresh option is still enabled).
32
DD2P
DD0
= V
Electrical Specifications – I
Configuration
, I
DDQ
and I
x4, x8, x16
DD1
DD6
x4, x8
x4, x8
/2
, I
x16
x16
DD3P(SLOW)
will increase by this amount if T
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD2N
C
≤ 85°C:
, I
DDL
DD2Q
DD
2Gb: x4, x8, x16 DDR2 SDRAM
= +1.8V ±0.1V, V
limits increase) on IT-option devices when
must be derated by 4%; I
, I
-187E
DD3N
tbd
tbd
tbd
tbd
tbd
tbd
DD2P
, I
DD3P(FAST)
DD6
must be derated by 20%; I
-25E/-25
and I
185
220
250
330
12
© 2006 Micron Technology, Inc. All rights reserved.
8
DD6
REF
, I
DD7
= V
must be derated by
DD4R
DD
C
must be derated by
DDQ
< 85°C and the 2x
-3/-3E
, I
165
200
225
300
DD4R
12
DD4W
Parameters
/2.
8
C
≤ +85°C.
and I
, and I
Units
DD5W
mA
mA
mA
DD3P
DD5W