MT47H128M16RT-3:C Micron Technology Inc, MT47H128M16RT-3:C Datasheet - Page 80

• Manufacturer Part Number: MT47H128M16RT-3:C
• Description: IC DDR2 SDRAM 2GB 667HZ 84FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H128M16RT-3:C

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (128M x 16)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Write Recovery
Power-Down Mode
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. F 12/10 EN
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 36 (page 78).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 65 (page 112).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing
nanoseconds) by
integer; WR (cycles) =
known operation or incompatibility with future versions may result.
Active power-down (PD) mode is defined by bit M12, as shown in Figure 36. PD mode
enables the user to determine the active power-down mode, which determines perform-
ance versus power savings. PD mode bit M12 does not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I
power mode is defined in the DDR2 I
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
t
CK (in nanoseconds) and rounding up a noninteger value to the next
t
WR (ns)/
80
t
CK (ns). Reserved states should not be used as an un-
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Specifications and Conditions table.
2Gb: x4, x8, x16 DDR2 SDRAM
DD3P
Mode Register (MR)
© 2006 Micron Technology, Inc. All rights reserved.
normal and I
t
WR (in
DD3P
low-