UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 22

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
UJA1069_3
Product data sheet
Fig 12. States of the INH/LIMP pin
6.9 Wake-up input
INH/LIMP:
ILEN = 1
ILC = 1
HIGH
When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a
default LOW level. The pin can be set to HIGH according to the state diagram.
When pin INH/LIMP is used as limp-home output, a pull-up resistor to V
default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe
mode.
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has
an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are
selected via the WAKE Sample Control bit (WSC):
If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the
level of bit WSC.
The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the
System Status register reflect the actual status of pin WAKE. The WAKE port can be
disabled by clearing the WEN bit in the System Configuration register.
•
•
state change via SPI
Continuous sampling (with an internal clock) if the bit is set
Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see
This is to save bias current within the external switches in low-power operation. Two
repetition times are possible, 16 ms and 32 ms.
power-on
OR (enter Start-up mode after
wake-up reset, external reset
OR enter Restart mode
OR enter Sleep mode
state change via SPI
or V1 undervoltage)
Rev. 03 — 10 September 2007
OR enter Fail-safe mode
state change via SPI
state change via SPI
INH/LIMP:
floating
ILC = 1/0
ILEN = 0
OR enter Fail-safe mode
state change via SPI
state change via SPI
001aad178
LIN fail-safe system basis chip
INH/LIMP:
ILEN = 1
ILC = 0
LOW
UJA1069
© NXP B.V. 2007. All rights reserved.
BAT42
ensures a
Figure
22 of 64
13.