UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 29

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
Table 6.
[1]
UJA1069_3
Product data sheet
Bit
11 to 8
7
6
5
4
3
2
0
1
The RSS bits are updated with each reset event and not cleared. The last reset event is captured.
System Status register bit description
Symbol
RSS[3:0]
-
LWS
EWS
WLS
TWS
SDMS
ENS
PWONS
6.12.5 System Diagnosis register
This register allows diagnosis information to be read back from the SBC. This register can
be read in all modes.
Description
Reset Source
reserved
LIN Wake-up Status
Edge Wake-up Status
WAKE Level Status
Temperature Warning
Status
Software Development
Mode Status
Enable Status
Power-on reset Status
[1]
Rev. 03 — 10 September 2007
…continued
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Function
power-on reset; first connection of BAT42 or BAT42 below
power-on voltage threshold or RSTN was forced LOW
externally
cyclic wake-up out of Sleep mode
low V1 supply; V1 has dropped below the selected reset
threshold
V1 current above threshold within Standby mode while
watchdog OFF behavior and reset option (V1CMC bit) are
selected
V3 voltage is down due to overload occurring during Sleep
mode
SBC successfully left Flash mode
SBC ready to enter Flash mode
reserved for SBCs with CAN transceiver
LIN wake-up event
local wake-up event (via pin WAKE)
wake-up out of Fail-safe mode
watchdog overflow
watchdog not initialized in time; t
watchdog triggered too early; window missed
illegal SPI access
interrupt not served within t
reserved for SBCs with CAN transceiver
LIN wake-up detected; cleared upon read
no LIN wake-up
pin WAKE negative edge detected; cleared upon read
pin WAKE no edge detected
pin WAKE above threshold
pin WAKE below threshold
chip temperature exceeds the warning limit
chip temperature is below the warning limit
Software Development mode on
Software Development mode off
pin EN output activated (V1-related HIGH level)
pin EN output released (LOW level)
power-on reset; cleared after a successfully entered
Normal mode
no power-on reset
LIN fail-safe system basis chip
RSTN(INT)
WD(init)
UJA1069
exceeded
© NXP B.V. 2007. All rights reserved.
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