UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 56

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
Table 26.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
[2]
[3]
[4]
[5]
UJA1069_3
Product data sheet
Symbol
Interrupt output; pin INTN
t
Oscillator
f
INTN
osc
vj
= 40 C to +150 C; V
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
SPI timing is guaranteed for V
at these lower voltages a lower maximum SPI communication speed must be observed.
t
1 k /1 k /10 nF; 1 k /2 k /6.8 nF; 1 k /open/1 nF; see
bit
1
2
= selected bit time, depends on LSC bit; 50 s or 96 s (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R
3
4
=
=
Dynamic characteristics
t
-------------------------------
t
------------------------------- -
bus rec min
bus rec max
Parameter
interrupt release
oscillator frequency
2 t
2 t
bit
bit
BAT42
Fig 24. SPI timing
SDO
SCS
SCK
BAT42
SDI
= 5.5 V to 52 V; V
voltages down to 5 V. For V
floating
…continued
X
Conditions
after SPI has read out the
Interrupt register
t
lead
Rev. 03 — 10 September 2007
BAT14
X
t
SCKH
= 5.5 V to 27 V; V
Figure 25
t
su
MSB
T
BAT42
cyc
t
SCKL
MSB
t
h
voltages down to 4.5 V the guaranteed SPI timing values double, so
and
Figure
BAT42
26.
[1]
V
BAT14
Min
2
460.8
LIN fail-safe system basis chip
1 V; unless otherwise specified. All
t
DOV
Typ
-
512
LSB
t
lag
LSB
UJA1069
Max
-
563.2
© NXP B.V. 2007. All rights reserved.
t
SSH
1
/R
001aaa405
floating
2
/C
X
1
):
56 of 64
Unit
kHz
s