AN983BX-BG-T-V3 Infineon Technologies, AN983BX-BG-T-V3 Datasheet - Page 39

• Manufacturer Part Number: AN983BX-BG-T-V3
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BX-BG-T-V3

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BXBGTV3; SP000103413

Table 10
Mode
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
Table 11
Clock Short Name
9.1.1
Offset
00h
04h
08h
0ch
Data Sheet
b31------------------------------------------------b16 b15------------------------------------------------------------b0
Device ID*
Status
Base Class Code Subclass
------
Registers Access Types (cont’d)
Registers Clock Domains
AN983B/BX Configuration Registers Descriptions
Symbol Description Hardware (HW)
ro
rv
lhsc
llsc
lhmk
llmk
ihsc
ilsc
ihmk
ilmk
ien
lor
rwsc
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Latch high signal at low-level, register
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
Differentiate the input signal (high-
>low) register cleared with written mask
Differentiate the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
------
Registers and Descriptors DescriptionAN983B/BX Configuration Registers
Description
39
Vendor ID*
-----------
Latency timer Cache line size
Command
Description Software (SW)
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is read and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Revision# Step#
Rev. 1.81, 2005-12-15
AN983B/BX