AN983BX-BG-T-V1 Infineon Technologies, AN983BX-BG-T-V1 Datasheet
AN983BX-BG-T-V1
Specifications of AN983BX-BG-T-V1
AN983BXBGTV1XP
SP000075554
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AN983BX-BG-T-V1 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... ISAC , ITAC ® ® ® QUAT , QuadFALC , SCOUT ® ® 10BaseV , 10BaseVX are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft ® Corporation, Linux of Linus Torvalds, Visio Incorporated. ® ® ® , ASP , DigiTape , DuSLIC ® ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 12 Layout Guide (Rev. 1.0B ...
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List of Figures Figure 1 System Diagram of the AN983B/ ...
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List of Tables Table 1 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The AN983B/ high performance PCI Fast Ethernet controller with a integrated physical layer interface for 10BASE-T and 100BASE-TX applications. The AN983BX is the environmentally friendly “green” package version. The AN983B/BX was designed with advanced CMOS technology to provide a glueless 32-bit bus master interface for PCI, boot ROM interface, and CSMA/CD protocol for Fast Ethernet, as well as the physical media interface for 100BASE-TX of IEEE802 ...
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Supports for IEEE802.3x flow control • IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX • PCI Specification 2.2 compliant • ACPI and PCI power management Ver.1.1 compliant • Supports PC99 wake on LAN FIFO • Provides two independent long FIFOs ...
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Miscellaneous • Provides 128-pin QFP/LQFP packages for PCI/mini-PCI interfaces • 3.3 V power supply with 5 V/3.3 V I/O tolerance 4 Block Diagram CR/CSR/XR Registers PCI I/F Control Boot ROM I/F EEPROM I/F Figure 2 Block Diagram of the AN983B/BX ...
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Pin Assignment Diagram bra 13 1 bra 14 2 bra 15 3 VAAR 4 TST3 5 RXIN 6 RXIP 7 GNDR 8 TST0 9 TST1 10 TST2 GNDREEF 14 RIBB 15 VAAREF 16 XTLN ...
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Pin Type and Buffer Type Abbreviations Standardized abbreviations: Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. AO Output. ...
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Pin Description Table 3 Pin Definitions and Functions Pin or Ball Name No. PCI Interface 24 INTA# 25 RST# 27 PCI-CLK 29 GNT# 30 REQ# 31 PME# Data Sheet Pin Buffer Function Type Type O/D PCI Interrupt Request AN983B/BX ...
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Table 3 Pin Definitions and Functions (cont’d) Pin or Ball Name No. 33, 34 AD-31, 30 35, 36 AD-29, 28 38, 39 AD-27, 26 40, 41 AD-25, 24 46, 47 AD-23, 22 49, 50 AD-21, 20 51, 53 AD-19, 18 ...
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Table 3 Pin Definitions and Functions (cont’d) Pin or Ball Name No. 92 Clk-run BOOTROM/EEPROM Interface 98 BrA0 99 BrA1 100 BrA2 101 BrA3 106 BrA4 108 BrA5 109 BrA6 110 BrA7 112 BrA8 113 BrA9 126 BrA10 127 BrA11 ...
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Table 3 Pin Definitions and Functions (cont’d) Pin or Ball Name No. 128 Mtxen 109 MtxD0 110 MtxD1 112 MtxD2 113 MtxD3 108 Mtxerr 101 Mdio 120 Mrxdv 100 Mcrs 116 MrxD0 117 MrxD1 118 MrxD2 119 MrxD3 99 Mcol ...
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Table 3 Pin Definitions and Functions (cont’d) Pin or Ball Name No. 102 Led-Act (Led-lnk/act) 103 Led-10Lnk (Led-fd/col) 104 Led-100Lnk (Led-speed) 105 Led-Fd/Col 95 Vaux 96 Vcc-detect Data Sheet Pin Buffer Function Type Type O 4 LED Mode: LED Display ...
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Table 3 Pin Definitions and Functions (cont’d) Pin or Ball Name No. 97 PMEP Digital Power Pins V V 26, 32, 42 ss-pci ss-IR V 45, 52, 62, ss-3 71, 80, 82, 91, 107 V V 23, 28, ...
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Functional Descriptions 7.1 Initialization Flow The flow of initialize AN983B/BX is shown as below. Need setting media type? Read EEPROM from CSR9 Set Physical address (CSR25, 26) Need setting Figure 4 Initialization Flow 7.2 Network Packet Buffer Management 7.2.1 ...
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Ring structure There are two buffers per descriptor in the ring structure. Support receives early interrupt. CSR3 or CSR4 Descriptor Pointer End of Ring Figure 5 Ring Structure of Frame Buffer • Chain structure There is only one buffer ...
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The Point of Descriptor Management OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access • Transmit Descriptor Pointers next packet to be transmitted own bit=2, packet1 and packet 2 are ...
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Figure 8 Receive Pointers for Descriptor Management Data Sheet Descriptor 0 Data Buffer Packet Packet 1 0 Packet 2 22 AN983B/BX ...
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Transmit Scheme and Transmit Early Interrupt 7.3.1 Transmit Flow The flow of packet transmit is shown as below. AN983B read descriptor available descriptor(own=1) read data and put into tx fifo no deferring and greater than tx threshold DO TRANSMIT ...
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FIFO-to-host memory operation (1st packet) Transmit enable place the 2nd packet data into host memory check point FIFO-to-host memory operation (2nd packet) place the 3rd packet data into host ...
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FIFO operation FIFO-to-host memory operation interrupt driver read header higher layer process driver read the rest data receive early interrupt driver read header(early) higher layer process(early) driver read the rest data Figure 12 Receive Data Flow (without ...
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MAC Operation In the MAC (Media Access Control) portion of AN983B/BX, it incorporates the essential protocol requirements for operating as an IEEE802.3 and Ethernet compliant node. Table 4 Format Field Preamble Start Frame Delimiter Destination Address Source Address Length/Type ...
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Transceiver Operation In the transceiver portion of the AN983B/BX, it integrates the IEEE802.3u compliant functions of PCS (physical coding sub-layer), PMA (physical medium attachment) sub-layer, PMD (physical medium dependent) sub-layer for 100BASE-TX, the IEEE802.3 compliant functions of Manchester encoding/decoding, ...
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Receiving Operation Regarding the 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA, and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns ratio ...
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Full Duplex and Half Duplex Operation of Transceiver The transceiver can operate for either full duplex or half duplex network application. In full duplex, both transmission and reception can be operated simultaneously. Under full duplex mode, collision (COL) signal is ...
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MAC Control Frame and PAUSE Frame Figure 14 MAC Control Frame Format The MAC Control frame is distinguished from other MAC frames only by their Length/Type field identifier. The MAC Control Opcode defined in MAC Control Frame format for PAUSE ...
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Figure 15 PAUSE Operation Receive State Diagram Data Sheet Functional Descriptions 31 AN983B/BX Rev. 1.81, 2005-12-15 ...
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LED Display Operation The AN983B/BX provides 2 kinds of LED display mode; the detailed descriptions about the operation are described in the PIN Description section. 7.6.1 First Mode – 3 LED Displays for • 100 Mbit/s(on Mbit/s(off) ...
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Magic Packet, it will assert the PME# signal (drive to low) to indicate receiving a wake up frame as well as to set the PME status bit (the bit 15 of CSR20). 7.9 ACPI Power Management Function The AN983B/BX ...
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Table 5 Power State (cont’d) Device PCI-Bus Function Context State State D2 B0, B1, Configuration B2 maintained and Rx D3hot B0, B1, Configuration lost, full B2 initialization required upon return to D0 D3cold B3 All configurations lost. Power-on ...
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General EEPROM Format Description Table 6 Connection Type Definition Offset Length 0xA 20 2 ...
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Data Sheet AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT Full Duplex 100BaseTx Full Duplex 100BaseFx Full Duplex 36 AN983B/BX General EEPROM Format Description Rev. 1.81, 2005-12-15 ...
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Registers and Descriptors Description There are three kinds of registers designed for AN983B/BX. They are AN983B/BX configuration registers, PCI control/status registers, and Transceiver control/status registers. The AN983B/BX configuration registers are used to initialize and configure the AN983B/BX for identifying ...
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AN983B/BX Configuration Registers Table 7 Registers Address Space Module Base Address xxxxx 1200 0000 Table 8 Registers Overview Register Short Name Register Long Name LID_CR0 Loaded Identification Number CSD_CR1 Configuration Command and Status CC_CR2 Class Code and Revision Number ...
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Table 10 Registers Access Types (cont’d) Mode Symbol Description Hardware (HW) Read only ro Register is set by HW (register between input and output -> one cycle delay) Read virtual rv Physically, there is no new register, the input of ...
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Offset b31------------------------------------------------b16 b15------------------------------------------------------------b0 10h Base I/O address 14h Base memory address 18h~24h Reserved 28h ROM-im* Address space offset* 2ch Subsystem ID* 30h Boot ROM base address 34h Reserved 38h Reserved 3ch Max_Lat* Min_Gnt* 40h Reserved 80h Signature of AN983B/BX c0h ...
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CSD_CR1 Configuration Command and Status Field Bits Type SPE 31 rw SES 30 rw SMA 29 rw STA 28 rw Res 27 ro SDST 26:25 ro SDPR 24 rw SFBB 23 ro Res 22: Res 19:9 ...
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Field Bits Type CPE 6 rw Res 5:3 ro CMO 2 rw CMSA 1 rw CIOSA 0 rw rw: Read and Write able. ro: Read able only Class Code and Revision Number CC_CR2 Class Code and Revision Number Field Bits ...
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LT_CR3 Latency Timer Field Bits Type Res 31: 15:8 rw CLS 7:0 rw I/O Base Address IOBA_CR4 I/O Base Address Field Bits Type IOBA 31:8 rw Res 7:1 ro IOSI 0 ro Data Sheet Registers and Descriptors DescriptionAN983B/BX ...
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Memory Base Address MBA_CR5 Memory Base Address Field Bits Type MBA 31:10 rw Res 9:1 ro IOSI 0 ro Card Information Structure For Card bus. Note: Automatically recalled from EEPROM when PCI reset is deserted. CIS_CR10 Card Information Structure Field ...
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Field Bits Type SID 31:16 ro SVID 15:0 ro Boot ROM Base Address 256 Bytes ROM size. BRBA_CR12 Boot ROM Base Address Field Bits Type BRBA 31:17 rw Res 16:1 ro BRE 0 rw This register should be initialized before ...
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Field Bits Type Res 31 7:0 ro Configuration Interrupt CI_CR15 Configuration Interrupt Field Bits Type ML 31: 23: 15 7:0 rw Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers Description Reserved Capabilities ...
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Driver Space for Special Purpose DS_CR16 Driver Space for Special Purpose Field Bits Type Res 31: 15:8 rw Res 7:0 ro Signature of AN983B/BX Hard wired register, read only SIG_CR32 Signature Field Bits Type DID 31:16 ro VID ...
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Power Management Register 0 PMR0_CR48 Power Management Register 0 Field Bits Type PMES 31:27 ro D2S 26 ro D1S 25 ro AUXC 24:22 ro DSI 21 ro Res 20 ro PMEC 19 ro VER 18:16 ro NIP 15:8 ro CAPID ...
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Power Management Register 1 PMR1_CR49 Power Management Register 1 Field Bits Type Res 31:16 ro PMES 15 rw* DSCAL 14:13 ro DSEL 12:9 rw PME_En 8 rw Res 7:2 ro PWRS 1:0 rw Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration ...
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Read and Write clear Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers 50 AN983B/BX Rev. 1.81, 2005-12-15 ...
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PCI Control/Status Registers Table 12 Registers Address Space Module Base Address 0000 0000 Table 13 Registers Overview Register Short Name Register Long Name PAR_CSR0 PCI Access Register TDR_CSR1 Transmit Demand Register RDR_CSR2 Receive Demand Register RDB_CSR3 Receive Descriptor Base ...
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Table 14 Registers Access Types Mode Symbol Description Hardware (HW) read/write rw Register is used as input for the HW read r Register is written by HW (register between input and output -> one cycle delay) write w read/write rwh ...
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PCI Access Register PAR_CSR0 PCI Access Register Field Bits Type Res 31:25 ro MWIE 24 rw* MRLE 23 rw* Res 22 ro MRME 21 rw* Res 20:19 ro TAP 18:17 rw* Res 16 ro Data Sheet Registers and Descriptors DescriptionPCI ...
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Field Bits Type CAL 15:14 rw* PBL 13:8 rw* BLE 7 rw* DSL 6:2 rw* BAR 1 rw* SWR 0 rw* Transmit Demand Register TDR_CSR1 Transmit Demand Register Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Cache Alignment, Address ...
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Field Bits Type TPDM 31:0 rw* Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Transmit Poll Demand When written any value in suspended state, trigger read-tx-descriptor process and check the own-bit, if own-bit = 1, then start transmit process. ...
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Receive Demand Register RDR_CSR2 Receive Demand Register Field Bits Type RPDM 31:0 rw* Receive Descriptor Base Address RDB_CSR3 Receive Descriptor Base Address Field Bits Type SAR 31:2 rw* RBND 1:0 ro Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Offset ...
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Transmit Descriptor Base Address TDB_CSR4 Transmit Descriptor Base Address Field Bits Type SAT 31:2 rw* TBND 1 before writing the transmit process should be stopped Status Register SR_CSR5 Status Register Field Bits Type Res 31:26 ro BET ...
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Field Bits Type TS 22: 19:17 ro NISS 16 ro/lh AISS 15 ro/lh Res 14 ro FBE 13 ro/lh Res 12 ro Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Transmit State Report the current transmission state ...
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Field Bits Type GPTT 11 ro/lh Res 10 ro RWT 9 ro/lh RPS 8 ro/lh RDU 7 ro/lh RCI 6 ro/lh TUF 5 ro/lh Res 4 ro TJT 3 ro/lh TDU 2 ro/lh TPS 1 ro/lh Data Sheet Registers and ...
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Field Bits Type TCI 0 ro/lh Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Transmit Completed Interrupt Note: lh: High Latching and cleared by writing means a frame transmission is completed while bit 31 of TDES1 ...
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Network Access Register NAR_CSR6 Network Access Register Field Bits Type Res 31: rw* Res 20 ro SQE 19 rw* Res 18: 15:14 rw rw** OM 11:10 rw** Data Sheet Registers ...
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Field Bits Type Res 9 rw*** PR 6 rw*** SBC 5 rw** Res rw*** Res Res 0 ro Interrupt Enable Register IER_CSR7 Interrupt Enable Register Data Sheet Registers ...
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Field Bits Type Res 31:17 ro NIE 16 rw AIE 15 rw Res 14 ro FBEIE 13 rw Res 12 ro GPTIE 11 rw Res 10 ro RWTIE 9 rw RSIE 8 rw RUIE 7 rw RCIE 6 rw TUIE ...
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Lost Packet Counter LPC_CSR8 Lost Packet Counter Field Bits Type Res 31:17 ro LPCO 16 ro/lh LPC 15:0 ro/lh Serial Port Register SPR_CSR9 Serial Port Register Field Bits Type Res 31:20 ro MDI 19 rw MMC 18 rw MDO 17 ...
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Field Bits Type MDC 16 rw Res 15 ro SRC 14 rw SWC 13 rw Res 12 ro SRS 11 rw Res 10:4 ro SDO 3 ro SDI 2 rw SCLK 1 rw SCS 0 rw General-Purpose Timer TMR_CSR11 General-Purpose ...
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WCSR_CSR13 Wake-up Control/Status Register Field Bits Type Res 31 ro CRCT 30 rw WP1E 29 rw WP2E 28 rw WP3E 27 rw WP4E 26 rw WP5E 25 rw Res 24:18 ro LinkOFF 17 rw LinkON 16 rw Res 15:11 ro ...
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Field Bits Type MPR 1 rw1c LSC 0 rw1c CSR14, WPDR – Wake-up Pattern Data Register All six wake-up patterns filtering information are programmed through WPDR register. The filtering information is as follows: Offset 31-24 0000h Wake-up pattern 1 mask ...
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To load the whole wake-up frame-filtering information, consecutive 25 long words write operation to CSR14 should be done. Watchdog Timer WTMR_CSR15 Watchdog Timer Field Bits Type Res 31:29 ro MRXCK 28 r Res 27:6 r RWR 5 rw RWD ...
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Assistant CSR5 (Status Register 2) ACSR5_CSR16 Assistant CSR5 (Status Register 2) Field Bits Type TEIS 31 ro/lh REIS 30 ro/lh LCS 29 ro/lh TDIS 28 ro/lh Res 27 ro PFR 26 ro/lh Res 25:17 ro ANISS 16 ro/lh AAISS 15 ...
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Field Bits Type FBE 13 ro/lh Res 12 ro GPTT 11 ro/lh Res 10 ro RWT 9 ro/lh RPS 8 ro/lh RDU 7 ro/lh RCI 6 ro/lh TUF 5 ro/lh Res 4 ro TJT 3 ro/lh Data Sheet Registers and ...
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Field Bits Type TDU 2 ro/lh TPS 1 ro/lh TCI 0 ro/lh Bit14 to 0 are the same as the status register of CSR5. You can access those status bits through either CSR5 or CSR16. Data Sheet Registers and Descriptors ...
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Assistant CSR7 (Interrupt Enable Register 2) ACSR7_CSR17 Assistant CSR7 (Interrupt Enable Register 2) Field Bits Type TEIE 31 rw REIE 30 rw LCIE 29 rw TDIE 28 rw Res 27 ro PFRIE 26 rw Res 25:17 ro ANISE 16 rw ...
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Field Bits Type RCIE 6 rw TUIE 5 rw Res 4 ro TJTTIE 3 rw TDUIE 2 rw TPSIE 1 rw TCIE 0 rw Bit14 to 0 are the same as the interrupt enable register of CSR7. You can access ...
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Field Bits Type ATS 27 rw PPE 26 rw PCI_R 4_3L 23 rw RFS 22:21 rw CRD APM 18 rw LWS 17 rw Res 16:8 ro Data Sheet Registers and ...
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Field Bits Type D3A 7 rw RWP 6 rw PAUSE 5 rw RTE 4 rw DRT 3:2 rw SINT 1 rw ATUR 0 rw Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description D3_APM D3_cold APM_mode_en for PC99 Certification It ...
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PCI Bus Performance Counter PCIC_CSR19 PCI Bus Performance Counter Field Bits Type CLKCNT 31:16 ro* Res 15:8 ro DWCNT 7:0 ro* Power Management Command and Status (The same register value mapping to CR49-PMR1) PMCSR_CSR20 Power Management Command and Status Field ...
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Field Bits Type DSCAL 14:13 ro DSEL 12:9 ro PME_En 8 ro Res 7:2 ro PWRS 1:0 ro Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Data_Scale Indicates the scaling factor to be used when interpreting the value of ...
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Current Working Transmit Descriptor Pointer WTDP_CSR21 Current Working Transmit Descriptor Pointer Field Bits Type WTDP 31:0 ro Current Working Receive Descriptor Pointer WRDP_CSR22 Current Working Receive Descriptor Pointer Field Bits Type WRDP 31:0 ro Data Sheet Registers and Descriptors DescriptionPCI ...
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Transmit Burst Count/Time-out TXBR_CSR23 Transmit Burst Count/Time-out Field Bits Type Res 31:21 ro TBCNT 20:16 rw TTO 11:0 rw Flash ROM (also the boot ROM) Port FROM_CSR24 Flash ROM (also the boot ROM) Port Field Bits Type BON 31 rw ...
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Physical Address Register 0 Automatically recall from EEPROM PAR0_CSR25 Physical Address Register 0 Field Bits Type PAB3 31:24 rw PAB2 23:16 rw PAB1 15:8 rw PAB0 7:0 rw Physical Address Register 1 Automatically recall from EEPROM PAR1_CSR26 Physical Address Register ...
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MAR0_CSR27 Multicast Address Register 0 Field Bits Type MAB3 31:24 rw MAB2 23:16 rw MAB1 15:8 rw MAB0 7:0 rw Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Offset AC H Description Multicast Address Byte ...
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Multicast Address Register 1 MAR1_CSR28 Multicast Address Register 1 Field Bits Type MAB7 31:24 rw MAB6 23:16 rw MAB5 15:8 rw MAB4 7:0 rw MAR0 and MAR1 are readable, but can be written only if the receive state is in ...
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Unicast Address Register 0 UAR0_CSR_29 Unicast Address Register 0 Field Bits Type UAB3 31:24 rw UAB2 23:16 rw UAB1 15:8 rw UAB0 7:0 rw Unicast Address Register 1 UAR1_CSR_30 Unicast Address Register 1 Field Bits Type UAB7 31:24 rw UAB6 ...
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Field Bits Type SPEED LINK 29 ro Res 28: Res 25:3 ro OpMode 2:0 rw Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Network Speed Status 0 , 10M B ...
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PHY Registers(Accessed by CSR9 MDI/MMC/MDO/MDC) Table 15 Registers Address Space Module Base Address PHY 0000 0000 Table 16 Registers Overview Register Short Name Register Long Name R0 Register 0(MII Control) R1 Register 1(Status) R2 Register 2 R3 Register 3 ...
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Table 17 Registers Access Types (cont’d) Mode Symbol Description Hardware (HW) Latch low, llmk Latch high signal at low-level, register mask clearing cleared on read Interrupt high, ihsc Differentiate the input signal (low- self clearing >high) register cleared on read ...
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Field Bits Type SPEED 13 rw ANE RAN 9 rwsc Res 6:0 ro SC: Self Clearing Reset: Reset this port only. This will cause the following: ...
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Collision test: Always 0 because collision signal is not implemented. Register 1 Status R1 Register 1(Status) Field Bits Type 100BT4 15 ro 100BFD 14 ro 100BHD 13 ro 10FD 12 ro 10HD 11 ro 100BT2FD 10 ro 100BT2HD 9 ro ...
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Field Bits Type ro ro Register 2 and 3 Each PHY has an identifier, which is assigned to the device. The identifier contains a total of 32 bits, ...
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Register 2 R2 Register 2 Field Bits Type PHY_ID 15:0 ro Register 3 R3 Register 3 Field Bits Type PHY_ID0 15:10 ro PHY_ID1 9:4 ro PHY_ID2 3:0 ro This uses the OUI of Infineon-ADMtek, device type of 1 and rev ...
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Register 4 R4 Register 4 Field Bits Type Res NI1 12:11 ro PAUSE 10 rw NI2 9 ro 100BFD 8 rw 100BHD 7 rw 10BFD 6 rw 10BHD 4:0 ...
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Register 5 The register is used to view the advertised capabilities of the link partner once autonegotiation is complete. The contents of this register should not be relied upon unless register 1 bit 5 is set (autoneg complete). After negotiation ...
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Register 6 R6 Register 6 Field Bits Type Res 15:5 ro PDF 4 ro, lh LPNP ro, lh LPAA 0 ro LH: Latch High Data Sheet Registers and Descriptors DescriptionPHY Registers(Accessed by CSR9 ...
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Descriptors and Buffer Management Table 18 Registers Overview Register Short Name Register Long Name RDES0 RDES0 RDES1 RDES1 RDES2 RDES2 RDES3 RDES3 TDES0 TDES0 TDES1 TDES1 TDES2 TDES2 TDES3 TDES3 The register is addressed wordwise. Standard abbreviations: Table 19 ...
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Table 19 Registers Access Types (cont’d) Mode Symbol Description Hardware (HW) Interrupt high, ihsc Differentiate the input signal (low- self clearing >high) register cleared on read Interrupt low, ilsc Differentiate the input signal (high- self clearing >low) register cleared on ...
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Field Bits Type OWN 30: 13: ...
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Field Bits Type Data Sheet Registers and Descriptors DescriptionDescriptors and Buffer Management Description Overflow This bit is valid only in last descriptor. 97 AN983B/BX Rev. 1.81, 2005-12-15 ...
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RDES1 RDES1 RDES1 Field Bits Type Res 31:26 ro RER 25 rw RCH 24 rw Res 23:22 ro RBS2 21:11 rw RBS1 10:0 rw RDES2 RDES2 RDES2 Field Bits Type RBA1 31:0 rw RDES3 Data Sheet Registers and Descriptors DescriptionDescriptors ...
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RDES3 RDES3 Field Bits Type RBA2 31:0 rw 9.4.2 Transmit Descriptor Descriptions The AN983B/BX provides receive and transmit descriptors for packet buffering and management. Descriptor addresses must be longword alignment Table 21 Transmit Descriptor Table TDES0 Own ...
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Field Bits Type Res 13: 6:3 rw Res TDES1 ...
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TDES2 TDES2 TDES2 Field Bits Type BA1 31:0 rw TDES3 TDES3 TDES3 Field Bits Type BA2 31:0 rw Data Sheet Registers and Descriptors DescriptionDescriptors and Buffer Management Offset 08 H Description Buffer Address 1 Without any limitation on the transmission ...
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Electrical Specifications and Timings 10.1 Absolute Maximum Ratings Table 22 Min-Max Ratings Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection Attention: Stresses above the max. values listed here may cause permanent damage to the ...
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Table 25 Flash/EEPROM Interface DC Specifications Parameter Input LOW Voltage Input HIGH Voltage Input Leakage Current Output LOW Voltage Output HIGH Voltage Input Pin Capacitance 10.3 AC Specifications Table 26 PCI Signaling AC Specifications for 3.3 V Parameter Switching Current ...
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Figure 16 PCI Clock Waveform Table 28 PCI Timings Parameter Access time – bused signals Access time – point to point Float to Active Delay Active to Float Delay Input Set up Time to Clock – bused signals Input Set ...
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CLK INPUT Figure 17 PCI Timings Table 29 Flash Interface Timings Parameter Read cycle time Chip enable access time Address access time Output enable access time CE low to active output OE low to active output CE high to active ...
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Table 29 Flash Interface Timings (cont’d) Parameter OE high hold time CE pulse width WE pulse width WE high width Data setup time Data hold time Byte load cycle time Byte load cycle time out ADDRESS CS# WE# DATA Figure ...
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ADDRESS CS# OE# DATA Figure 19 Flash Read Timings Table 30 EEPROM Interface Timings (AC/AD) Parameter Serial Clock Frequency Delay from CS High to SK High T Delay from SK Low to CS Low T Setup Time ...
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CS CLK DI Figure 20 Serial EEPROM Timing Data Sheet Tecss Tecsh Tedts Tedth 108 AN983B/BX Electrical Specifications and Timings Tecsl Rev. 1.81, 2005-12-15 ...
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MII Interface Timing TX_CLK TXD<3:0>,TX_EN, TX_ER 0 ns Min 25 ns MAX Figure 21 Transmit Signal Timing Relationships at the MII RX_CLK RXD<3:0>,RX_DV, RX_ER Figure 22 Receive Signal Timing Relations at the MII Data Sheet Electrical Specifications and Timings 10 ...
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MDC MDIO Figure 23 MDIO Sourced by STA MDC MDIO 0 ns Min 300 ns MAX Figure 24 MDIO Sourced by PHY Data Sheet 10 ns MIN 110 AN983B/BX Electrical Specifications and Timings V ih(min) V il(max) V ih(min) V ...
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Package Outlines E Figure 25 Package outline for the AN983B / AN983BL Table 31 Dimensions for 128 -pin PQFP Package (AN983B/X) Symbol Description A Overall Height A1 Stand Off b Lead Width c Lead Thickness D Terminal Dimension 1 ...
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Table 32 Dimensions for 128 -pin LQFP Package (AN983BLX) Symbol Description A Overall Height A1 Stand Off b Lead Width c Lead Thickness D Terminal Dimension 1 D1 Package Body 1 E Terminal Dimension 2 E1 Package Body 2 e1 ...
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Layout Guide (Rev. 1.0B) Table 33 Layout Guide Revision History Revision Date Revision October, 2000 1.0b 12.1 Placement • Keep the distance as short as possible between Centaur-P and transformer, as well as transformer and RJ45. • Make crystal ...
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Figure 26 Ground Via Trace Arrangement V 12.3 and GND CC V • power CC V – Avoid unnecessary trace to IC’s and devices keep these traces as short and wide. CC – Power trace width > 40 mils (if ...
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RJ45 Chassis Ground Figure 28 Ground Plane Arrangement Data Sheet VCC PLANE UNDER Transformer System Ground 115 AN983B/BX Layout Guide (Rev. 1.0B) CHIP Rev. 1.81, 2005-12-15 ...
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... Published by Infineon Technologies AG ...