AN983BX-BG-T-V1 Infineon Technologies, AN983BX-BG-T-V1 Datasheet - Page 52

• Manufacturer Part Number: AN983BX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BXBGTV1; AN983BXBGTV1XP; SP000075554

Table 14
Mode
read/write
read
write
read/write
hardware
affected
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
9.2.1
Data Sheet
Registers Access Types
PCI Control/Status Registers Description
Symbol Description Hardware (HW)
rw
r
w
rwh
rwv
ro
rv
lhsc
llsc
lhmk
llmk
ihsc
ilsc
ihmk
ilmk
ien
lor
rwsc
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register can be modified by HW
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Latch high signal at low-level, register
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
Differentiate the input signal (high-
>low) register cleared with written mask
Differentiate the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
Registers and Descriptors DescriptionPCI Control/Status Registers
52
Description Software (SW)
Register is read and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
Register is writable by SW
Register can be modified by HW, but the
priority SW versus HW has to be specified
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is read and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Rev. 1.81, 2005-12-15
AN983B/BX