AN983BX-BG-T-V1 Infineon Technologies, AN983BX-BG-T-V1 Datasheet - Page 67

• Manufacturer Part Number: AN983BX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BXBGTV1; AN983BXBGTV1XP; SP000075554

Field
MPR
LSC
CSR14, WPDR – Wake-up Pattern Data Register
All six wake-up patterns filtering information are programmed through WPDR register. The filtering information is
as follows:
Offset
0000h
0004h
0008h
000ch
0010h
0014h
0018h
001ch
0020h
0024h
0028h
002ch
0030h
0034h
0038h
003ch
0040h
0044h
0048h
004ch
0050h
0054h
0058h
005ch
0060h
1. Offset value is from 0-255 (8-bit width).
Data Sheet
31-24
Wake-up pattern 1 mask bits 31:0
Wake-up pattern 1 mask bits 63:32
Wake-up pattern 1 mask bits 95:64
Wake-up pattern 1 mask bits 127:96
CRC16 of pattern 1
Wake-up pattern 2 mask bits 31:0
Wake-up pattern 2 mask bits 63:32
Wake-up pattern 2 mask bits 95:64
Wake-up pattern 2 mask bits 127:96
CRC16 of pattern 2
Wake-up pattern 3 mask bits 31:0
Wake-up pattern 3 mask bits 63:32
Wake-up pattern 3 mask bits 95:64
Wake-up pattern 3 mask bits 127:96
CRC16 of pattern 3
Wake-up pattern 4 mask bits 31:0
Wake-up pattern 4 mask bits 63:32
Wake-up pattern 4 mask bits 95:64
Wake-up pattern 4 mask bits 127:96
CRC16 of pattern 4
Wake-up pattern 5 mask bits 31:0
Wake-up pattern 5 mask bits 63:32
Wake-up pattern 5 mask bits 95:64
Wake-up pattern 5 mask bits 127:96
CRC16 of pattern 5
Bits
1
0
Type
rw1c
rw1c
23-16
Description
Magic Packet Received
Note: rw1c: Read only and Write one cleared.
1
Link Status Changed
Note: rw1c: Read only and Write one cleared.
1
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
by writing 1 or upon power-up reset. It is not affected by a hardware
or software reset
is cleared by writing 1 or upon power-up reset. It is not affected by
a hardware or software reset
, indicates AN983B/BX has received a magic packet. It is cleared
, indicates AN983B/BX has detected a link status change event. It
67
15-8
Reserved
Reserved
Reserved
Reserved
Reserved
7-0
Wake-up pattern 1 offset
Wake-up pattern 2 offset
Wake-up pattern 3 offset
Wake-up pattern 4 offset
Wake-up pattern 5 offset
Rev. 1.81, 2005-12-15
AN983B/BX