IC SWITCH DUAL SPST 8VSSOP

74LVC2G66DC,125

Manufacturer Part Number74LVC2G66DC,125
DescriptionIC SWITCH DUAL SPST 8VSSOP
ManufacturerNXP Semiconductors
Series74LVC
TypeAnalog Switch
74LVC2G66DC,125 datasheet
 

Specifications of 74LVC2G66DC,125

Package / Case8-VFSOP (0.091", 2.3mm Width)FunctionSwitch
Circuit2 x SPST - NOOn-state Resistance6 Ohm
Voltage Supply SourceSingle SupplyVoltage - Supply, Single/dual (±)1.65 V ~ 5.5 V
Current - Supply0.1µAOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountSwitch ConfigurationSPST
On Resistance (max)34 Ohm (Typ) @ 1.95 VOn Time (max)4.6 ns (Typ) @ 1.95 V
Off Time (max)3.8 ns (Typ) @ 1.95 VSupply Voltage (max)5.5 V
Supply Voltage (min)1.65 VMaximum Power Dissipation250 mW
Maximum Operating Temperature+ 125 CMounting StyleSMD/SMT
Minimum Operating Temperature- 40 CSwitch Current (typ)0.0001 mA @ 5.5 V
Package8VSSOPMaximum On Resistance195@1.95V Ohm
Maximum Propagation Delay Bus To Bus0.8(Typ)@1.95V|0.4(Typ)@2.7V|0.3(Typ)@3.6V|0.2(Typ)@5.5V nsMaximum Low Level Output Current50 mA
Maximum Turn-off Time3.8(Typ)@1.95V nsMaximum Turn-on Time4.6(Typ)@1.95V ns
Switch ArchitectureSPSTPower Supply TypeSingle
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names74LVC2G66DC-G
74LVC2G66DC-G
935274429125
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74LVC2G66
Bilateral switch
Rev. 5 — 16 June 2010
1. General description
The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device.
The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire V
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at V
6.5 Ω (typical) at V
6 Ω (typical) at V
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Enable input accepts voltages up to 5.5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
range from 1.65 V to 5.5 V.
CC
= 2.7 V
CC
= 3.3 V
CC
= 5 V
CC
Product data sheet

74LVC2G66DC,125 Summary of contents

  • Page 1

    Bilateral switch Rev. 5 — 16 June 2010 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC2G66DP −40 °C to +125 °C 74LVC2G66DC −40 °C to +125 °C 74LVC2G66GT −40 °C to +125 °C 74LVC2G66GD −40 °C to +125 °C 74LVC2G66GM 4. Marking Table 2. Marking codes ...

  • Page 3

    ... NXP Semiconductors Fig 3. Logic diagram (one switch) 6. Pinning information 6.1 Pinning 74LVC2G66 GND 4 001aaa529 Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC2G66 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 74LVC2G66 Product data sheet Fig 5. Pin configuration SOT833-1 terminal 1 index area 001aai248 Fig 7 ...

  • Page 4

    ... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT996-2 and SOT833 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

  • Page 5

    ... NXP Semiconductors 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb Δt/ΔV input transition rise and fall rate [1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0 ...

  • Page 6

    ... NXP Semiconductors Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance C OFF-state S(OFF) capacitance C ON-state S(ON) capacitance [1] All typical values are measured at T amb [2] These typical values are measured at V 10.1 Test circuits ...

  • Page 7

    ... NXP Semiconductors 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Symbol Parameter Conditions R ON resistance V = GND to V ON(peak) I (peak resistance V = GND; see ON(rail) I (rail 1.95 V ...

  • Page 8

    ... NXP Semiconductors 10.3 ON resistance test circuit and graphs GND Fig 10. Test circuit for measuring ON resistance (Ω (4) (3) (2) ( 0.4 0.8 1.2 = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 12. ON resistance as a function of input voltage; ...

  • Page 9

    ... NXP Semiconductors (Ω) 11 (1) 9 (2) ( 0.5 1.0 1.5 2.0 = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 14. ON resistance as a function of input voltage 2 (Ω) = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = − ...

  • Page 10

    ... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nY; pd see Figure enable time nZ; en see Figure disable time nZ; see dis Figure power dissipation pF capacitance ...

  • Page 11

    ... NXP Semiconductors Σ{(C ) × V × sum of the outputs. L S(ON 11.1 Waveforms and test circuit Measurement points are given in Logic levels: V and V are typical output voltage levels that occur with the output load Fig 17. Input (nY or nZ) to output (nZ or nY) propagation delays nE input ...

  • Page 12

    ... NXP Semiconductors negative positive Test data is given in Table 11. Definitions for test circuit Load resistor Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 19. Test circuit for measuring switching times Table 11. ...

  • Page 13

    ... NXP Semiconductors 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T Symbol Parameter THD total harmonic distortion −3 dB frequency response f (−3dB) α isolation (OFF-state) iso 74LVC2G66 Product data sheet Conditions kΩ pF kHz; see ...

  • Page 14

    ... NXP Semiconductors Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T Symbol Parameter V crosstalk voltage ct Xtalk crosstalk Q charge injection inj 74LVC2G66 Product data sheet …continued Conditions between digital inputs and switch pF MHz ns; see 600 Ω; C between switches ...

  • Page 15

    ... NXP Semiconductors 11.3 Test circuits Test conditions 1. 1.4 V (p-p 2 (p-p 2.5 V (p-p 4 (p-p Fig 20. Test circuit for measuring total harmonic distortion Adjust f voltage to obtain 0 dBm level at output. Increase f i Fig 21. Test circuit for measuring the frequency response when switch is in ON-state ...

  • Page 16

    ... NXP Semiconductors G Fig 23. Test circuit for measuring crosstalk voltage (between digital inputs and switch 600 Ω 20 log ( log Fig 24. Test circuit for measuring crosstalk between switches 74LVC2G66 Product data sheet nY/nZ nZ/nY logic 50 Ω 600 Ω input 0.5V 0. 0.1 μ 600 Ω ...

  • Page 17

    ... NXP Semiconductors G a. Test circuit logic input (nE) b. Input and output pulse definitions = ΔV × inj O L ΔV = output voltage variation generator resistance. gen V = generator voltage. gen Fig 25. Test circuit for measuring charge injection 74LVC2G66 Product data sheet gen nY/nZ nZ/nY ...

  • Page 18

    ... NXP Semiconductors 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 0.38 mm 1.1 0.25 0.00 0.75 0.22 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

  • Page 19

    ... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.85 0. 0.12 0.00 0.60 0.17 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 20

    ... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) ( UNIT max max 0.25 2.0 1.05 mm 0.5 0.04 0.17 1.9 0.95 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

  • Page 21

    ... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 3.1 mm 0.5 0.00 0.15 2.9 1.9 OUTLINE VERSION IEC SOT996 Fig 29. Package outline SOT996-2 (XSON8U) ...

  • Page 22

    ... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area 8 DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 1.65 mm 0.5 ...

  • Page 23

    ... NXP Semiconductors 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date 74LVC2G66 v.5 20100616 • Modifications: Conditions for I 74LVC2G66 v ...

  • Page 24

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 25

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC2G66 Product data sheet 15 ...

  • Page 26

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics 10.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 ...