LFXP3E-4T100I Lattice, LFXP3E-4T100I Datasheet - Page 179

• Manufacturer Part Number: LFXP3E-4T100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4T100I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
The various ports and their definitions for the True Dual Memory are included in Table 9-4. The table lists the corre-
sponding ports for the module generated by IPexpress and for the EBR RAM_DP_TRUE primitive.
Table 9-4. EBR-based True Dual Port Memory Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal would form the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-
bit bus, so it can easily cascade eight memories. However, if the memory size specified by the user requires more
than eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU external to the EBR blocks.
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 9-5.
Table 9-5. True Dual Port Memory Sizes for 9K Memory for LatticeECP/EC and LatticeXP Devices
Table 9-6 shows the various attributes available for True Dual Port Memory (RAM_DP_TRUE). Some of these attri-
butes are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
ClockA, ClockB
ClockEnA, ClockEnB
AddressA, AddressB
DataA, DataB
QA, QB
WEA, WEB
ResetA, ResetB
—
Memory Size
Dual Port
Generated Module
512 x 18
8K x 1
4K x 2
2K x 4
1K x 9
Port Name in
Input Data
DIA[17:0]
DIA[1:0]
DIA[3:0]
DIA[8:0]
Port A
DIA
CLKA, CLKB
DIA[y:0], DIB[y:0]
DOA[y:0], DOB[y:0]
WEA, WEB
RSTA, RSTB
CSA[2:0], CSB[2:0]
CEA, CEB
ADA[x:0], ADB[x:0]
Port Name in the EBR
Block Primitive
Input Data
DIB[17:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
Port B
DIB
Clock for PortA and PortB
Clock Enables for Port CLKA and CLKB
Address Bus Port A and Port B
Input Data Port A and Port B
Output Data Port A and Port B
Write Enable Port A and Port B
Reset for Port A and Port B
Chip Selects for Each Port
Output Data
DOA[17:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
Port A
DOA
9-14
Description
LatticeECP/EC and LatticeXP Devices
Output Data
DOB[17:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
Port B
DOB
Address Port A
[MSB:LSB]
ADA[12:0]
ADA[11:0]
ADA[10:0]
ADA[9:0]
ADA[8:0]
Memory Usage Guide
Rising Clock Edge
Active High
—
—
—
Active High
Active High
—
Active State
Address Port B
[MSB:LSB]
ADB[12:0]
ADB[11:0]
ADB[10:0]
ADB[9:0]
ADB[8:0]