LFXP3E-4T100I Lattice, LFXP3E-4T100I Datasheet - Page 227

• Manufacturer Part Number: LFXP3E-4T100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4T100I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
IDDRXB
This primitive will implement the input register block. The software defaults to CE Enabled unless otherwise speci-
fied. The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFB primi-
tive). The SCLK input should be connected to the system (FPGA) clock. The SCLK and CE inputs to this primitive
will be used primarily to synchronize the DDR inputs. DDRCLKPOL is an input from the DQS Clock Polarity tree.
This signal is generated by the DQS Transition detect circuit in the hardware. Figure 10-9 shows the primitive sym-
bol and the I/O ports.
Figure 10-9. IDDRXB Symbol
Table 10-6 provides a description of all I/O ports associated with the IDDRXB primitive.
Table 10-6. IDDRXB Ports
Note:
1. The DDRCLKPOL input to IDDRXB should be connected to the DDRCLKPOL output of DQSBUFB.
ODDRXB
The ODDRXB primitive implements both the write and the tristate functions. This primitive is used to output DDR
data and the DQS strobe to the memory. The CKP and CKN can also be generated using this primitive. All the
DDR output tristate implementations are also implemented using the same primitive.
Figure 10-10 shows the ODDRXB primitive symbol and its I/O ports.
D
ECLK
LSR
SCLK
CE
DDRCLKPOL
QA
QB
Port Name
I/O
O
O
I
I
I
I
I
I
DDR data
The phase shifted DQS should be connected to this input
Reset
System CLK
Clock enable
DDR clock polarity signal
Data at the positive edge of the CLK
Data at the negative edge of the CLK
D
ECLK
LSR
SCLK
CE
DDRCLKPOL
IDDRXB
10-8
Definition
QA
QB
LatticeECP/EC and LatticeXP
DDR Usage Guide