LFXP3E-4T100I Lattice, LFXP3E-4T100I Datasheet - Page 240

• Manufacturer Part Number: LFXP3E-4T100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4T100I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Appendix B. Verilog Example for DDR Input and Output Modules
module ddr_mem (dq, dqs, clk, reset, uddcntl, read, datain_p, datain_n, dqsc, prmbdet, lock,
ddrclkpol, clk90, dqstri_p, dqstri_n, datatri_p, datatri_n, dataout_p, dataout_n, ddrclk);
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
inout [7:0] dq/* synthesis IO_TYPE="SSTL25_II"*/;
inout dqs/* synthesis IO_TYPE="SSTL25_II"*/;
--clk is the core clock and clk90 is the 90 degree phase shifted clock coming from the PLL
input clk, clk90;
input reset, uddcntl, read;
input [7:0] dataout_p, dataout_n;
input [7:0] datatri_p, datatri_n;
input dqstri_p, dqstri_n;
output [7:0] datain_p;
output[7:0] datain_n;
output dqsc, prmbdet, lock, ddrclkpol;
output ddrclk /* synthesis IO_TYPE="SSTL25D_II"*/ ;
wire vcc_net,gnd_net;
wire dqsbuf, dqsdel, clk, ddrclkpol_sig;
wire [7:0] ddrin, ddrout, tridata;
wire dqsout, tridqs, dqsin, ddrclk;
assign vcc_net = 1'b1;
assign gnd_net = 1'b0;
assign ddrclkpol = ddrclkpol_sig;
//-------Bidirectional Buffers ------------------------------------------------------
BB bidiInst0 (.I(ddrout[0]), .T(tridata[0]), .O(ddrin[0]), .B(dq[0]));
BB bidiInst1 (.I(ddrout[1]), .T(tridata[1]), .O(ddrin[1]), .B(dq[1]));
BB bidiInst2 (.I(ddrout[2]), .T(tridata[2]), .O(ddrin[2]), .B(dq[2]));
BB bidiInst3 (.I(ddrout[3]), .T(tridata[3]), .O(ddrin[3]), .B(dq[3]));
BB bidiInst4 (.I(ddrout[4]), .T(tridata[4]), .O(ddrin[4]), .B(dq[4]));
BB bidiInst5 (.I(ddrout[5]), .T(tridata[5]), .O(ddrin[5]), .B(dq[5]));
BB bidiInst6 (.I(ddrout[6]), .T(tridata[6]), .O(ddrin[6]), .B(dq[6]));
BB bidiInst7 (.I(ddrout[7]), .T(tridata[7]), .O(ddrin[7]), .B(dq[7]));
//Bidirectional Strobe, DQS
BB bidiInst8(.I(dqsout), .T(tridqs), .O(dqsin), .B(dqs));
//------------------------------------------------------------------------------------
//-----------DDR Input ---------------------------------------------------------------
DQSBUFB
DQSDLL U9 (.CLK(clk), .UDDCNTL(uddcntl), .RST(reset), .DQSDEL(dqsdel), .LOCK(lock));
IDDRXB
UL0
U8
.LSR(reset), .QA(datain_p[0]), .QB(datain_n[0]));
.DQSC(dqsc), .PRMBDET(prmbdet), .DQSO(dqsbuf));
(.DQSI(dqsin),
(.D(ddrin[0]),
.CLK(clk),
.ECLK(dqsbuf),
10-21
.READ(read),
.SCLK(clk),
LatticeECP/EC and LatticeXP
.DQSDEL(dqsdel),
.CE(vcc_net),
DDR Usage Guide
.DDRCLK-
.DDRCLK-