LFXP3E-4T100I Lattice, LFXP3E-4T100I Datasheet - Page 388

• Manufacturer Part Number: LFXP3E-4T100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4T100I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

PCB Layout Recommendations
Lattice Semiconductor
for BGA Packages
Figure 14-11. CAM Artwork Screen Shots, Example #2, 256-ball caBGA
Layer 1 Primary
Layer 2 GND
Layer 3 Power
Layer 4 Secondary
PCB Fabrication Cost and Design Rule Considerations
PCB fabrication cost is a key consideration for many electronics products. By reviewing the IC device package ball
density and pitch, I/O signal requirements of your application, and the manufacturing constraints of your PCB fabri-
cation facility you can better weigh the trade-offs between design decisions.
Choosing the best package for your application involves answering a few questions:
• What is the driving factor in the application? The smallest possible form factor or a low PCB cost?
• How many I/O signals does the application require?
• What PCB layer stack up will provide the best I/O density within budget?
• What layout design rules does the printed-circuit board (PCB) vendor support?
• How many PCB layers does the budget allow?
As the ball pitch becomes smaller with each new BGA generation, new PCB fabrication techniques and signal via
type have been developed to handle the complexities. Micro vias, laser vias, filled, buried and blind vias, even bur-
ied and plated over vias. Complex boards use a combination of most of these.
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