LFXP3E-4T100I Lattice, LFXP3E-4T100I Datasheet - Page 228

• Manufacturer Part Number: LFXP3E-4T100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4T100I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 10-10. ODDRXB Symbol
Table 10-7 provides a description of all I/O ports associated with the ODDRXB primitive.
Table 10-7. ODDRXB Ports
Notes:
Memory Read Implementation
The LatticeECP/EC and LatticeXP devices contain a variety of features to simplify implementation of the read por-
tion of a DDR interface:
The LatticeECP/EC and LatticeXP device data sheets detail these circuit elements.
Three primitives in the Lattice ispLEVER
DLL represents the DLL used for calibration. The IDDRXB primitive represents the DDR input registers and clock
domain transfer registers. Finally, the DQSBUFB represents the DQS delay block and the clock polarity control
logic. These primitives are explained in more detail in the following sections of this document. Figure 10-11 illus-
trates how to hook these primitives together to implement the read portion of a DDR memory interface. The DDR
Software Primitives section describes each of the primitives and its instantiation in more detail. Appendices A and B
provide example code to implement the complete I/O section of a memory interface within a LatticeECP/EC or Lat-
ticeXP device.
1. LSR should be held low during DDR Write operation. By default, the software will be implemented CE High
2. DDR output and tristate registers do not have CE support. LSR is available for the tristate DDRX mode
3. CE and LSR support is available for the regular (non-DDR) output mode.
4. When asserting reset during DDR writes, it is important to keep in mind that this would only reset the FFs
• DLL compensated DQS delay elements
• DDR input registers
• Automatic DQS to system clock domain transfer circuitry
and LSR low.
(while reading). The LSR will default to set when used in the tristate mode.
and not the latches.
CLK
DA
DB
LSR
Q
Port Name
®
design tools represent the capability of these three elements. The DQS-
CLK
DA
DB
LSR
I/O
I
I
I
I
I
System CLK
Data at the positive edge of the clock
Data at the negative edge of the clock
Reset
DDR data to the memory
ODDRXB
10-9
Definition
Q
LatticeECP/EC and LatticeXP
DDR Usage Guide